| 2002 | Improved Test Monitor Circuit in Power Pin DfT. | Rodger Schuttert, Frans G. M. de Jong, Ben Kup |
| 2002 | Controlling Peak Power During Scan Testing. | Ranganathan Sankaralingam, Nur A. Touba |
| 2002 | Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. | Sagar S. Sabade, D. M. H. Walker |
| 2002 | Challenges of Mixed-Signal Board Design and Test. | G. Roberts |
| 2002 | On Test Data Volume Reduction for Multiple Scan Chain Designs. | Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz |
| 2002 | Reconfiguration Technique for Reducing Test Time and Test Data Volume in Illinois Scan Architecture Based Designs . | Amit R. Pandey, Janak H. Patel |
| 2002 | Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis. | Sule Ozev, Alex Orailoglu |
| 2002 | Analog and Mixed Signal BIST: Too Much, Too Little, Too Late? | Adam Osseiran, William De Wilkins, Barry Baril, Sassan Tabatabaei, Fidel Muradali, Ken Posse, Lee Song |
| 2002 | Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus. | Chee-Kian Ong, Kwang-Ting (Tim) Cheng |
| 2002 | Eigen-Signatures for Regularity-based IDDQ Testing. | Yukio Okuda |
| 2002 | A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. | Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa |
| 2002 | Testing High-Speed SoCs Using Low-Speed ATEs. | Mehrdad Nourani, James Chin |
| 2002 | Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? | Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark |
| 2002 | Design for Testability and Testing of IEEE 1149.1 Tap Controller. | Subhasish Mitra, Edward J. McCluskey, Samy Makar |
| 2002 | SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? | Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim |
| 2002 | Debating the Future of Burn-In. | Edward J. McCluskey, Subhasish Mitra, Bob Madge, Peter C. Maxwell, Phil Nigh, Mike Rodgers |
| 2002 | Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies. | Robert Madge, Manu Rehani, Kevin Cota, W. Robert Daasch |
| 2002 | Very Low Voltage Testing of SOI Integrated Circuits. | Eric W. MacDonald, Nur A. Touba |
| 2002 | Testing and Diagnosing Embedded Content Addressable Memories. | Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu |
| 2002 | Diagnosis of Sequence-Dependent Chips. | Chien-Mo James Li, Edward J. McCluskey |
| 2002 | Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. | Rahul Kundu, R. D. (Shawn) Blanton |
| 2002 | Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? | Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham |
| 2002 | Instruction-Based Self-Testing of Processor Cores. | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
| 2002 | Test Vector Compression Using EDA-ATE Synergies. | Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra |
| 2002 | Spectrum-Based BIST in Complex SOCs. | Ganapathy Kasturirangan, Michael S. Hsiao |