| 2002 | Test Vector Modification for Power Reduction during Scan Testing. | Seiji Kajihara, Koji Ishida, Kohei Miyase |
| 2002 | Performance Comparison of VLV, ULV, and ECR Tests. | Wanli Jiang, Eric Peterson |
| 2002 | Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. | Madhu K. Iyer, Kwang-Ting Cheng |
| 2002 | On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization. | Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2002 | Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation. | Shi-Yu Huang |
| 2002 | A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. | Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka |
| 2002 | Testing Static and Dynamic Faults in Random Access Memories. | Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor |
| 2002 | Measuring Stray Capacitance on Tester Hardware. | Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley |
| 2002 | Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions. | Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2002 | Scan-Path with Directly Duplicated and Inverted Duplicated Registers. | Michael Gssel, Egor S. Sogomonyan, Adit D. Singh |
| 2002 | Cluster-Based Test Architecture Design for System-on-Chip. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. | Aiman El-Maleh, Ali Al-Suwaiyan |
| 2002 | Exploiting Dominance and Equivalence using Fault Tuples. | Kumar N. Dwarakanath, R. D. (Shawn) Blanton |
| 2002 | On Using Efficient Test Sequences for BIST. | Ren David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2002 | Beyond CMOS. | B. Courtoi, Michael R. B. Forshaw |
| 2002 | Validation and Test of Network Processors and ASICs. | C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim |
| 2002 | A Self Calibrated ADC BIST Methodology. | Hung-Kai Chen, Chih-Hu Wang, Chau-Chin Su |
| 2002 | RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics. | Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu |
| 2002 | How Effective are Compression Codes for Reducing Test Data Volume? | Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina |
| 2002 | Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. | Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah |
| 2002 | Fault Models for Speed Failures Caused by Bridges and Opens. | Sreejit Chakravarty, Ankur Jain |
| 2002 | Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus. | Jos Vicente Calvano, Vladimir Castro Alves, Antonio Carneiro de Mesquita Filho, Marcelo Lubaszewski |
| 2002 | A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution? | Bill Bottoms, Lee Song, Paul Patton, Wilhelm Radermacher |
| 2002 | Innovations in Test Automation. | J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski |
| 2002 | Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. | Swarup Bhunia, Kaushik Roy |