| 2002 | Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. | Dilip K. Bhavsar, Richard A. Davies |
| 2002 | An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. | Luis Berrojo, Isabel Gonzlez, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia Lpez |
| 2002 | Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems. | Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet |
| 2002 | Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. | Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy |
| 2002 | Test Pattern Generation for Signal Integrity Faults on Long Interconnects. | Amir Attarha, Mehrdad Nourani |
| 2002 | Multi-GigaHertz Testing Challenges and Solutions. | Karim Arabi, Klaus-Dieter Hilliges, David C. Keezer, Sassan Tabatabaei |
| 2002 | Logic BIST and Scan Test Techniques for Multiple Identical Blocks. | Karim Arabi |
| 2002 | Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. | M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs |
| 2002 | Approximating Infinite Dynamic Behavior for DRAM Cell Defects. | Zaid Al-Ars, Ad J. van de Goor |
| 2002 | Wireless Test. | Robert C. Aitken, Mustapha Slamani, H. Ding, William R. Eisenstadt, Sanghoon Choi, John McLaughlin |
| 2001 | Resistive Opens in a Class of CMOS Latches: Analysis and DFT. | Antonio Zenteno, Vctor H. Champac |
| 2001 | A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen |
| 2001 | Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals. | Dong Xiang, Yi Xu |
| 2001 | An Evaluation of Pseudo Random Testing for Detecting Real Defects. | Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson |
| 2001 | MINVDD Testing for Weak CMOS ICs. | Chao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh |
| 2001 | On Diagnosing Path Delay Faults in an At-Speed Environment. | Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar |
| 2001 | Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. | Tek Jau Tan, Chung-Len Lee |
| 2001 | Current Measurement for Dynamic Idd Test. | Xiaoyun Sun, Bapiraju Vinnakota |
| 2001 | Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. | Egor S. Sogomonyan, Andrej A. Morosov, Jan Rzeha, Michael Gssel, Adit D. Singh |
| 2001 | RT-level Fault Simulation Based on Symbolic Propagation. | Ozgur Sinanoglu, Alex Orailoglu |
| 2001 | Test Scheduling for Minimal Energy Consumption under Power Constraints. | Tobias Schle, Albrecht P. Stroele |
| 2001 | Reducing Power Dissipation during Test Using Scan Chain Disable. | Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya |
| 2001 | ITRS Test Chapter 2001: We'll Tell You What We're Doing, You Tell Us What We Should Be Doing. | Mike Rodgers |
| 2001 | Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. | Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian |
| 2001 | On the Use of Fault Dominance in n-Detection Test Generation. | Irith Pomeranz, Sudhakar M. Reddy |