| 2001 | Multiple Scan Chain Design for Two-Pattern Testing. | Ilia Polian, Bernd Becker |
| 2001 | Self-Testable Pipelined ADC with Low Hardware Overhead. | Eduardo J. Peralas, Gloria Huertas, Adoracin Rueda, Jos L. Huertas |
| 2001 | Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. | Ivan de Pal, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden |
| 2001 | A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. | Chintan Patel, Jim Plusquellic |
| 2001 | Reliability Beyond GHz. | Pete O'Neill, Ron Richmond, Mike Tripp, Barbara Vasquez, Art Wager, Zeev Weinberg |
| 2001 | Breaking Correlation to Improve Testability. | Kelly A. Ockunzzi, Christos A. Papachristou |
| 2001 | A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. | Muhammad Nummer, Manoj Sachdev |
| 2001 | Automatic Generation of Diagnostic March Tests. | Dirk Niggemeyer, Elizabeth M. Rudnick |
| 2001 | Design of Parameterizable Error-Propagating Space Compactors for Response Observation. | Andrej A. Morosov, Michael Gssel, Krishnendu Chakrabarty, Bhargab B. Bhattacharya |
| 2001 | Tools for the Characterization of Bipolar CML Testability. | Ginette Mont, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst |
| 2001 | Flash Memory Disturbances: Modeling and Test. | Mohammad Gh. Mohammad, Kewal K. Saluja |
| 2001 | Design of Redundant Systems Protected Against Common-Mode Failures. | Subhasish Mitra, Edward J. McCluskey |
| 2001 | Design Diversity for Concurrent Error Detection in Sequential Logic Circuts. | Subhasish Mitra, Edward J. McCluskey |
| 2001 | Efficient Transparency Extraction and Utilization in Hierarchical Test. | Yiorgos Makris, Vishal Patel, Alex Orailoglu |
| 2001 | Diagnosis of Tunneling Opens. | Chien-Mo James Li, Edward J. McCluskey |
| 2001 | Yield Optimization and Its Relation to Test. | Tracy Larrabee, Jon Colbum |
| 2001 | Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses. | Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng |
| 2001 | High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement. | Mohammad Athar Khalil, Chin-Long Wey |
| 2001 | Compression Technique for Interactive BIST Application. | Douglas Kay, Samiha Mourad |
| 2001 | Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. | Abhijit Jas, C. V. Krishna, Nur A. Touba |
| 2001 | Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip. | Vikram Iyengar, Krishnendu Chakrabarty |
| 2001 | A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs. | Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng |
| 2001 | An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. | Jiun-Lang Huang, Kwang-Ting Cheng |
| 2001 | On Improving the Accuracy Of Multiple Defect Diagnosis. | Shi-Yu Huang |
| 2001 | Testing of Dynamic Logic Circuits Based on Charge Sharing. | Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton |