| 2001 | Average Leakage Current Estimation of CMOS Logic Circuits. | Jos Pineda de Gyvez, Eric van de Wetering |
| 2001 | SPIRIT: A Highly Robust Combinational Test Generation Algorithm. | Emil Gizdarski, Hideo Fujiwara |
| 2001 | A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. | Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
| 2001 | Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal |
| 2001 | A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-Chip. | Aiman El-Maleh, Esam Khan, Saif al Zahir |
| 2001 | Semi-Formal Test Generation for a Block of Industrial DSP. | Julia Dushina, Mike Benjamin, Daniel Geist |
| 2001 | Soft Errors and Tolerance for Soft Errors. | Jim Chung, N. Derhacobian, Jean Gasiot, Michael Nicolaidis, David Towne, Raoul Velazco |
| 2001 | Testable Sequential Circuit Design: A Partition and Resynthesis Approach. | Richard M. Chou, Kewal K. Saluja |
| 2001 | Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. | Yue-Tsang Chen, Chauchin Su |
| 2001 | Enabling Embedded Memory Diagnosis via Test Response Compression. | John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare |
| 2001 | Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. | Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu |
| 2001 | Electrically Induced Stimuli For MEMS Self-Test. | Benot Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois |
| 2001 | Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. | Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer |
| 2001 | Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? | Henry Chang, Steve Dollens, Gordon W. Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham |
| 2001 | Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. | Anshuman Chandra, Krishnendu Chakrabarty |
| 2001 | IP and Automation to Support IEEE P1500. | Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti |
| 2001 | Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the Rescue. | Bill Bottoms, Jim Chung, Bernd Koenemann, Glenn Shirley, Lisa Spainhower |
| 2001 | Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. | Dilip K. Bhavsar |
| 2001 | Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. | Thomas S. Barnett, Adit D. Singh, Victor P. Nelson |
| 2001 | High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. | Xiaoliang Bai, Sujit Dey |
| 2001 | A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. | Florence Azas, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell |
| 2001 | Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs. | Amir Attarha, Mehrdad Nourani |
| 2001 | Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. | M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana |
| 2001 | An Efficient Methodology for Generating Optimal and Uniform March Tests. | Sultan M. Al-Harbi, Sandeep K. Gupta |
| 2001 | Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. | Magdy S. Abadir, Juhong Zhu, Li-C. Wang |