| 2000 | Do I Need this Tool for My Chips to Work? | Fidel Muradali, Andr Ivanov |
| 2000 | Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. | Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski |
| 2000 | Fault Escapes in Duplex Systems. | Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey |
| 2000 | Word Voter: A New Voter Design for Triple Modular Redundant Systems. | Subhasish Mitra, Edward J. McCluskey |
| 2000 | Invariance-Based On-Line Test for RTL Controller-Datapath Circuits. | Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu |
| 2000 | Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. | Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee |
| 2000 | SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. | Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | PROBE: A PPSFP Simulator for Resistive Bridging Faults. | Chul Young Lee, D. M. H. Walker |
| 2000 | On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
| 2000 | Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. | Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham |
| 2000 | An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops. | Seongwon Kim, Mani Soma, Dilip Risbud |
| 2000 | A Low-Speed BIST Framework for High-Performance Circuit Testing. | Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev |
| 2000 | Virtual Scan Chains: A Means for Reducing Scan Length in Cores. | Abhijit Jas, Bahram Pouya, Nur A. Touba |
| 2000 | Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs. | Sri Jandhyala, Hari Balachandran, Manidip Sengupta, Anura P. Jayasumana |
| 2000 | Testing, Verification, and Diagnosis in the Presence of Unknowns. | Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao |
| 2000 | RF/Analog Test of Circuits and Systems. | M. S. Huetmaker |
| 2000 | BSM2: Next Generation Boundary-Scan Master. | Frank P. Higgins, Rajagopalan Srinivasan |
| 2000 | Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. | Ilker Hamzaoglu, Janak H. Patel |
| 2000 | Functional Memory Faults: A Formal Notation and a Taxonomy. | Ad J. van de Goor, Zaid Al-Ars |
| 2000 | Low Power/Energy BIST Scheme for Datapaths. | Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian |
| 2000 | A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. | Jayabrata Ghosh-Dastidar, Nur A. Touba |
| 2000 | Detection of CMOS Defects under Variable Processing Conditions. | Amy Germida, James F. Plusquellic |
| 2000 | Testability Alternatives Exploration through Functional Testing. | Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi |
| 2000 | High-Level Observability for Effective High-Level ATPG. | Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero |
| 2000 | Low Power BIST via Non-Linear Hybrid Cellular Automata. | Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante |