| 2000 | Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. | Byungwoo Choi, D. M. H. Walker |
| 2000 | Integrating Logic BIST in VLSI Designs with Embedded Memories. | Vivek Chickermane, Scott Richter, Carl Barnhart |
| 2000 | A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. | Hugo Cheung, Sandeep K. Gupta |
| 2000 | DEFUSE: A Deterministic Functional Self-Test Methodology for Processors. | Li Chen, Sujit Dey |
| 2000 | Test Data Compression for System-on-a-Chip Using Golomb Codes. | Anshuman Chandra, Krishnendu Chakrabarty |
| 2000 | Detectability Conditions for Interconnection Open Defect. | Vctor H. Champac, Antonio Zenteno |
| 2000 | Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming. | Krishnendu Chakrabarty |
| 2000 | Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations. | Jos Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski |
| 2000 | High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. | Melvin A. Breuer |
| 2000 | Hidden Markov and Independence Models with Patterns for Sequential BIST. | Laurent Brhlin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault |
| 2000 | Test and Debug of Networking SoCs: A Case Study. | A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su |
| 2000 | General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. | Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu |
| 2000 | Self-Checking Circuits versus Realistic Faults in Very Deep Submicron. | Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal |
| 2000 | Thermal Testing: Fault Location Strategies. | Josep Altet, Antonio Rubio, Emmanuel Schaub, Stefan Dilhaire, Wilfrid Claeys |
| 2000 | ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. | Hussain Al-Asaad, John P. Hayes |
| 2000 | Silicon-on-Insulator Technology Impacts on SRAM Testing. | R. Dean Adams, Phil Shephard III |
| 1999 | Maximal Diagnosis of Interconnects of Random Access Memories. | Jun Zhao, Fred J. Meyer, Fabrizio Lombardi |
| 1999 | A Test Point Insertion Algorithm for Mixed-Signal Circuits. | Jinyan Zhang, Sam D. Huynh, Mani Soma |
| 1999 | A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units. | Kamran Zarrineh, Shambhu J. Upadhyaya |
| 1999 | A New Bare Die Test Methodology. | Zao Yang, Kwang-Ting Cheng, King L. Tai |
| 1999 | A Systematic DFT Procedure for Library Cells. | Jingjing Xu, Rahul Kundu, F. Joel Ferguson |
| 1999 | Hierarchical Test Generation for Analog Circuits Using Incremental Test Development. | Ramakrishna Voorakaranam, Abhijit Chatterjee |
| 1999 | Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. | Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs |
| 1999 | Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation. | Pramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee |
| 1999 | On the Comparison of IDDQ and IDDQ Testing. | Claude Thibeault |