| 1999 | Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
| 1999 | A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu |
| 1999 | A Current Integrator for BIST of Mixed-Signal ICs. | Sassan Tabatabaei, Andr Ivanov |
| 1999 | Test Metrics for Analog Parametric Faults. | Stephen K. Sunter, Naveena Nagi |
| 1999 | Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code. | Albrecht P. Stroele, Steffen Tarnick |
| 1999 | PADded Cache: A New Fault-Tolerance Technique for Cache Memories. | Philip P. Shirvani, Edward J. McCluskey |
| 1999 | Verification of Processor Microarchitectures. | Jian Shen, Jacob A. Abraham |
| 1999 | Partial Scan Using Multi-Hop State Reachability Analysis. | Sameer Sharma, Michael S. Hsiao |
| 1999 | Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs. | Josef Schmid, Joachim Knblein |
| 1999 | Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. | Marcelino B. Santos, Fernando M. Gonalves, Isabel C. Teixeira, Joo Paulo Teixeira |
| 1999 | Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. | Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin |
| 1999 | Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . | Maurizio Rebaudengo, Matteo Sonza Reorda |
| 1999 | A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits. | Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis |
| 1999 | TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. | Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha |
| 1999 | Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. | Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer |
| 1999 | An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. | Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
| 1999 | Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic. | Irith Pomeranz, Yervant Zorian |
| 1999 | On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | A Flexible Path Selection Procedure for Path Delay Fault Testing. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies. | Michael Nicolaidis |
| 1999 | Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. | Debashis Nayak, D. M. H. Walker |
| 1999 | Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test. | Michael A. Margolese, F. Joel Ferguson |
| 1999 | Design Technology Research and Education for Deep-Submicron Systems of the Next Century. | Hugo De Man |
| 1999 | Testing High Speed VLSI Devices Using Slower Testers. | Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar |
| 1999 | A Novel Test Methodology for MEMS Magnetic Micromotors. | Bruce C. Kim, Krishna Marella |