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IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
1998Distributed Generation of Weighted Random Patterns.Jacob Savir
1998Design of Phase Shifters for BIST Applications.Janusz Rajski, Jerzy Tyszer
1998Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model.Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
1998Synthesis of Zero-Aliasing Elementary-Tree Space Compactors.Bahram Pouya, Nur A. Touba
1998Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage.Irith Pomeranz, Sudhakar M. Reddy
1998On Synchronizing Sequences and Test Sequence Partitioning.Irith Pomeranz, Sudhakar M. Reddy
1998Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion.Ganapathy Parthasarathy, Michael L. Bushnell
1998Parallelism in Structural Fault Testing of Embedded Cores.Mehrdad Nourani, Christos A. Papachristou
1998Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores.Petra Nordholz, Dieter Treytnar, Jan Otterstedt, Hartmut Grabinski, Dirk Niggemeyer, T. W. Williams
1998Using Verification Technology for Validation Coverage Analysis and Test Generation.Dinos Moundanos, Jacob A. Abraham
1998Test Reuse at System Level.Jos M. Miranda, Scott Davidson, Peter Dziel, Saman Adham, Steve Millman
1998Analysis of Failures in Deep Submicron SRAM Cells.Pinaki Mazumder
1998Best Methods for At-Speed Testing?Peter C. Maxwell, Steve Baird, Wayne M. Needham, Al Crouch, Phil Nigh
1998Mixed Signal DFT at GHz Frequencies.Ralph Mason, Shing Ma
1998On Delay-Untestable Paths and Stuck-Fault Redundancy.Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell
1998Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan.Amitava Majumdar, Michio Komoda, Tim Ayres
1998Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm.Ovidio V. Maiuri, Will R. Moore
1998On Removing Redundant Faults in Synchronous Sequential Circuits.Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
1998Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1998Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits.Kyung Tek Lee, Clay Nordquist, Jacob A. Abraham
1998A Design for Testability Study on a High Performance Automatic Gain Control Circuit.Andreas Lechner, Andrew Richardson, B. Hermes, Michael J. Ohletz
1998Estimation of Error Detection Probability and Latency of Checking Methods for a Given Circuit under Check.Arsen Kuchukyan
1998Designing a Testable System on a Chip.Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz
1998Novel Single and Double Output TSC Berger Code Checkers.Xrysovalantis Kavousianos, Dimitris Nikolos
1998An Introduction to RF Testing: Device, Method and System.Jeffrey S. Kasten
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