| 1999 | Implication and Evaluation Techniques for Proving Fault Equivalence. | M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana |
| 1999 | From Design-for-Test to Design-for-Debug-and-Test: Analysis of Requirements and Limitations for 1149.1. | Gustavo R. Alves, Jos Manuel Martins Ferreira |
| 1999 | Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage. | Robert C. Aitken |
| 1999 | VTS 1999 Keynote Address Embedded Test OR External Test. | Vinod K. Agarwal |
| 1999 | The Limits of Digital Testing for Dynamic Circuits. | R. Dean Adams, Edmond S. Cooley |
| 1998 | Fault Detection and Diagnosis of Interconnects of Random Access Memories. | Jun Zhao, Fred J. Meyer, Fabrizio Lombardi |
| 1998 | Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips. | Kamran Zarrineh, Shambhu J. Upadhyaya, Philip Shephard III |
| 1998 | Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. | Hiroyuki Yotsuyanagi, Kozo Kinoshita |
| 1998 | Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits. | Heebyung Yoon, Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi |
| 1998 | A Novel Routing Algorithm for MCM Substrate Verification Using Single-Ended Prob. | Rongchang Yan, Bruce C. Kim |
| 1998 | A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. | Douglas Williams, F. Joel Ferguson, Tracy Larrabee |
| 1998 | On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. | Li-C. Wang, Magdy S. Abadir, Jing Zeng |
| 1998 | Decreasing the Sensitivity of ADC Test Parameters by Means of Wobbling. | R. de Vries, Augustus J. E. M. Janssen |
| 1998 | Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements. | Pramodchandran N. Variyam, Abhijit Chatterjee |
| 1998 | Nonlinear Analog DC Fault Simulation by One-Step Relaxation. | Michael W. Tian, Chuanjin Richard Shi |
| 1998 | Efficient Path Selection for Delay Testing Based on Partial Path Evaluation. | Seiichiro Tani, Mitsuo Teramoto, Tomoo Fukazawa, Kazuyoshi Matsuhiro |
| 1998 | Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing. | Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska, Fartoumi M. Hossein, Patrick Vincent |
| 1998 | Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits. | Charles E. Stroud, Joe K. Tannehill Jr. |
| 1998 | Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions. | Albrecht P. Stroele |
| 1998 | Improving Path Delay Fault Testability by Path Removal. | Uwe Sparmann, Lars Kller |
| 1998 | A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. | Egor S. Sogomonyan, Adit D. Singh, Michael Gssel |
| 1998 | An Approach to Modeling and Testing Memories and Its Application to CAMs. | Piotr R. Sidorowicz, Janusz A. Brzozowski |
| 1998 | A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. | Tsuyoshi Shinogi, Terumine Hayashi |
| 1998 | A New Path Tracing Algorithm with Dynamic Circuit Extraction for Sequential Circuit Fault Diagnosis. | Kazuki Shigeta, Toshio Ishiyama |
| 1998 | A Structural Approach for Space Compaction for Concurrent Checking and BIST. | Markus Seuring, Michael Gssel, Egor S. Sogomonyan |