| 1998 | A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults. | Dimitrios Karayiannis, Spyros Tragoudas |
| 1998 | Testing MEMS. | Jean-Michel Karam, Marcelo Lubaszewski, R. D. Shawn Blanton, Andrew Richardson |
| 1998 | Effect of Noise on Analog Circuit Testing. | Madhu K. Iyer, Michael L. Bushnell |
| 1998 | Built-In Self Testing of Sequential Circuits Using Precomputed Test Sets. | Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray |
| 1998 | COMPACT: A Hybrid Method for Compressing Test Data. | Masahiro Ishida, Dong Sam Ha, Takahiro J. Yamaguchi |
| 1998 | Fast Self-Recovering Controllers. | Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich |
| 1998 | Where We Might Stumble with Embedded-System Test. | Keerthi Heragu |
| 1998 | High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. | David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz |
| 1998 | New Techniques for Deterministic Test Pattern Generation. | Ilker Hamzaoglu, Janak H. Patel |
| 1998 | Validation and Test Problems for Cross Talk Noise. | Sandip Gupta, Craig Gleason |
| 1998 | Fault Models and Tests for Two-Port Memories. | Ad J. van de Goor, Said Hamdioui |
| 1998 | Sampling Techniques of Non-Equally Probable Faults in VLSI System. | Fernando M. Gonalves, Joo Paulo Teixeira |
| 1998 | Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. | T. A. Garca, Antonio J. Acosta, Jos L. Huertas, J. M. Mora, J. Ramos |
| 1998 | Low Cost Partial Scan Design: A High Level Synthesis Approach. | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe |
| 1998 | Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. | Debaleena Das, Nur A. Touba |
| 1998 | A Test Pattern Generation Methodology for Low-Power Consumption. | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
| 1998 | On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits. | Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda |
| 1998 | Transition Maximization Techniques for Enhancing the Two-Pattern Fault Coverage of Pseudorandom Test Pattern Generators. | Bruce F. Cockburn, Albert L.-C. Kwong |
| 1998 | Experimental Results for IDDQ and VLV Testing. | Jonathan T.-Y. Chang, Chao-Wen Tseng, Yi-Chin Chu, Sanjay Wattal, Mike Purtell, Edward J. McCluskey |
| 1998 | IDDQ Testing of Opens in CMOS SRAMs. | Vctor H. Champac, Jos Castillejos, Joan Figueras |
| 1998 | Performance Test Case Generation for Microprocessors. | Pradip Bose |
| 1998 | Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. | Debashis Bhattacharya |
| 1998 | Design-For-Testability for Switched-Current Circuits. | Florence Azas, Michel Renovell, Yves Bertrand, J.-C. Bodin |
| 1998 | A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. | Sultan M. Al-Harbi, Sandeep K. Gupta |
| 1997 | Static logic implication with application to redundancy identification. | Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel |