| 1997 | An on-line testable UART implemented using IFIS. | J. Yeandel, D. Thulborn, Simon Jones |
| 1997 | Using ATPG for clock rules checking in complex scan design. | Peter Wohl, John A. Waicukauski |
| 1997 | Automated test pattern generation for analog integrated circuits. | Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen |
| 1997 | Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. | Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi |
| 1997 | Exact probabilistic analysis of error detection for parity checkers. | Valery A. Vardanian |
| 1997 | Testing Embedded Cores Using Partial Isolation Rings. | Nur A. Touba, Bahram Pouya |
| 1997 | Obtaining High Fault Coverage with Circular BIST Via State Skipping. | Nur A. Touba |
| 1997 | A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. | Claude Thibeault |
| 1997 | Integrating on-chip temperature sensors into DfT schemes and BIST architectures. | Vladimr Szkely, Mrta Rencz, Bernard Courtois |
| 1997 | Methods to reduce test application time for accumulator-based self-test. | Albrecht P. Stroele, Frank Mayer |
| 1997 | Salvaging test windows in BIST diagnostic. | Jacob Savir |
| 1997 | Random pattern testability of memory control logic. | Jacob Savir |
| 1997 | Bridges in sequential CMOS circuits: current-voltage signatur. | Rosa Rodrguez-Montas, Joan Figueras |
| 1997 | Test of RAM-based FPGA: methodology and application to the interconnect. | Michel Renovell, Joan Figueras, Yervant Zorian |
| 1997 | Fault coverage of a long random test sequence estimated from a short simulation. | V. Prepin, R. David |
| 1997 | On n-detection test sequences for synchronous sequential circuits343. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. | Irith Pomeranz, Sudhakar M. Reddy |
| 1997 | A DFT Technique for Analog-to-Digital Converters with digital correction. | Eduardo J. Peralas, Adoracin Rueda, Jos L. Huertas |
| 1997 | On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. | Can kmen, Martin Keim, Rolf Krieger, Bernd Becker |
| 1997 | High-Level Synthesis for Orthogonal Sca. | Robert B. Norwood, Edward J. McCluskey |
| 1997 | Highly testable and compact single output comparator. | Cecilia Metra, Michele Favalli, Bruno Ricc |
| 1997 | ATPG for scan chain latches and flip-flops. | Samy Makar, Edward J. McCluskey |
| 1997 | SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. | Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee |
| 1997 | Assessing SRAM test coverage for sub-micron CMOS technologies. | V. Kim, T. Chen |
| 1997 | Critical hazard free test generation for asynchronous circuits. | Ajay Khoche, Erik Brunvand |