| 1997 | Polynomial Formal Verification of Multipliers. | Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor |
| 1997 | Self-exercising self testing k-order comparators. | Xrysovalantis Kavousianos, Dimitris Nikolos |
| 1997 | Testability of Sequential Circuits with Multi-Cycle False Path. | Priyank Kalla, Maciej J. Ciesielski |
| 1997 | A methodolgy for characterizing cell testability. | Alvin Jee, F. Joel Ferguson |
| 1997 | A Novel Solution for Chip-Level Functional Timing Verification. | Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham |
| 1997 | Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation. | Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz |
| 1997 | Incremental logic rectification. | Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng |
| 1997 | Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1997 | A linear code-preserving signature analyzer COPMISR. | Andrzej Hlawiczka, Michael Gssel, Egor S. Sogomonyan |
| 1997 | Built-in parametric test for controlled impedance I/Os. | T. Haulin |
| 1997 | A practical approach to instruction-based test generation for functional modules of VLSI processors. | Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada |
| 1997 | Diagnostic Test Pattern Generation for Sequential Circuits. | Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs |
| 1997 | Experimental fault analysis of 1 Mb SRAM chips. | Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki |
| 1997 | Disturb Neighborhood Pattern Sensitive Fault. | Ad J. van de Goor, Issam B. S. Tlili |
| 1997 | Using fault sampling to compute I | Yiming Gong, Sreejit Chakravarty |
| 1997 | Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS. | Nihal J. Godambe, Chuanjin Richard Shi |
| 1997 | Robust Sequential Fault Testing of Iterative Logic Arrays. | Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
| 1997 | An optimized BIST test pattern generator for delay testing. | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch |
| 1997 | Implicit test pattern generation constrained to cellular automata embedding. | Franco Fummi, Donatella Sciuto |
| 1997 | A new approach for testing artificial neural networks. | C. A. Fleischer, Lee A. Belfore II |
| 1997 | The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation. | Laura Farinetti, Pier Luca Montessoro |
| 1997 | Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor Circuits. | Christian Dufaza, Hassan Ihs |
| 1997 | Test methodology for embedded cores which protects intellectual property. | Kaushik De |
| 1997 | Switch-level modeling of feedback faults using global oscillation control. | Peter Dahlgren |
| 1997 | Cellular automata for deterministic sequential test pattern generation. | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda |