| 1996 | Optimization of analog IC test structures. | Eric Felt, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Hardware-Software Co-Design for Test: It's the Last Straw! | J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard |
| 1996 | A new digital test approach for analog-to-digital converter testing. | Mehdi Ehsanian, Bozena Kaminska, Karim Arabi |
| 1996 | Safety computations in integrated circuits. | Jean-Luis Dufour |
| 1996 | Isomorph-redundancy in sequential circuits. | Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya |
| 1996 | Faulty chip identification in a multi chip module system. | T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael |
| 1996 | A fault model for switch-level simulation of gate-to-drain shorts. | Peter Dahlgren, Peter Lidn |
| 1996 | An algebraic method for delay fault testing. | Sophie Crpaux-Motte, Mireille Jacomino, Ren David |
| 1996 | A new test pattern generation method for delay fault testing. | S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 1996 | Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. | Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham |
| 1996 | Quantitative analysis of very-low-voltage testing. | Jonathan T.-Y. Chang, Edward J. McCluskey |
| 1996 | A sampling technique for diagnostic fault simulation. | Sreejit Chakravarty |
| 1996 | Can Defect-Tolerant Chips Better Meet the Quality Challenge? | R. L. Campbell, P. Kuekes, David Y. Lepejian, Wojciech P. Maly, Michael Nicolaidis, Alex Orailoglu |
| 1996 | Board-Level BIST. | J. Braden, K. Brough, J. Evans, Martin P. McHugh, G. Young |
| 1996 | Full fault dictionary storage based on labeled tree encoding. | Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs |
| 1996 | Design of a fast, easily testable ALU. | R. D. (Shawn) Blanton, John P. Hayes |
| 1996 | H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. | Subhrajit Bhattacharya, Sujit Dey |
| 1996 | Scan insertion criteria for low design impact. | Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda |
| 1996 | Improvement of SRAM-based failure analysis using calibrated Iddq testing. | Hari Balachandran, D. M. H. Walker |
| 1996 | A novel built-in current sensor for I | Stephan P. Athan, David L. Landis, Sami A. Al-Arian |
| 1996 | Oscillation-test strategy for analog and mixed-signal integrated circuits. | Karim Arabi, Bozena Kaminska |
| 1996 | ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator. | Minesh B. Amin, Bapiraju Vinnakota |
| 1996 | Volume Manufacturing - ICs and Boards: DFT to the Rescue? | Robert C. Aitken, J. Hutcheson, N. Murthy, Phil Nigh, Nicholas Sporck |
| 1995 | Detectable perturbations: a paradigm for technology-specific multi-fault test generation. | Andrej Zemva, Franc Brglez |
| 1995 | Decompression of test data using variable-length seed LFSRs. | Nadime Zacharia, Janusz Rajski, Jerzy Tyszer |