| 1996 | Enhancing realistic fault secureness in parity prediction array arithmetic operators by I | Salvador Manich, Michael Nicolaidis, Joan Figueras |
| 1996 | Synchronization of large sequential circuits by partial reset. | Yuan Lu, Irith Pomeranz |
| 1996 | Optimal voltage testing for physically-based faults. | Yuyun Liao, D. M. H. Walker |
| 1996 | Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. | Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | The MCM's thermal testing. | Vladimir A. Koval, Dmytro V. Fedasyuk |
| 1996 | An unexpected factor in testing for CMOS opens: the die surface. | Haluk Konuk, F. Joel Ferguson |
| 1996 | BIST: Advantages or Limitations? | Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner |
| 1996 | Design Validation: Formal Verification vs. Simulation vs. Functional Testing. | Bernd Koenemann, J. Monzel, T. Powell, N. Saxena, K. Wagner |
| 1996 | Design of a fault tolerant 100 Gbits solid-state mass memory for satellite. | M. P. Kluth, Franois Simon, Jean-Yves Le Gall, E. Mller |
| 1996 | An analysis of fault partitioning algorithms for fault partitioned ATPG. | Robert H. Klenke, James H. Aylor, Joseph M. Wolf |
| 1996 | Low-cost diagnosis of defects in MCM substrate interconnections. | Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan |
| 1996 | Fault characterization of standard cell libraries using inductive contamination. | Jitendra Khare, Wojciech Maly, Nathan Tiday |
| 1996 | On the (non-)resetability of synchronous sequential circuits. | Martin Keim, Bernd Becker, Birgitta Stenner |
| 1996 | Is High Frequency Analog DFT Possible? | Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jrme Wojcik |
| 1996 | Generating deterministic unordered test patterns with counters. | Dimitrios Kagaris, Spyros Tragoudas |
| 1996 | An approach for testing programmable/configurable field programmable gate arrays. | Wei-Kang Huang, Fabrizio Lombardi |
| 1996 | On the diagnosis of programmable interconnect systems: Theory and application. | Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi |
| 1996 | Automatic test generation using genetically-engineered distinguishing sequences. | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | Segment delay faults: a new fault model. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1996 | Delay Fault Testing: How Robust are Our Models? | Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma |
| 1996 | A self-checking ALU design with efficient codes. | Steven S. Gorshe, Bella Bose |
| 1996 | March LR: a test for realistic linked faults. | Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik |
| 1996 | Current signatures [VLSI circuit testing]. | Anne E. Gattiker, Wojciech Maly |
| 1996 | An asynchronous totally self-checking two-rail code error indicator. | Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis |
| 1996 | On estimating bounds of the quiescent current for I | Antoni Ferr, Joan Figueras |