| 1996 | Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design. | Diego Vzquez, Jos L. Huertas, Adoracin Rueda |
| 1996 | On completely robust path delay fault testable realization of logic functions. | Valery A. Vardanian |
| 1996 | On minimizing the number of test points needed to achieve complete robust path delay fault testability. | Prasanti Uppaluri, Uwe Sparmann, Irith Pomeranz |
| 1996 | Applying two-pattern tests using scan-mapping. | Nur A. Touba, Edward J. McCluskey |
| 1996 | Test point insertion based on path tracing. | Nur A. Touba, Edward J. McCluskey |
| 1996 | Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). | Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici |
| 1996 | Test response compaction using arithmetic functions. | Albrecht P. Stroele |
| 1996 | Iterative test-point selection for analog circuits. | J. van Spaandonk, Tom A. M. Kevenaar |
| 1996 | Design and performance of CMOS TSPC cells for high speed pseudo random testing. | Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska |
| 1996 | Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems. | Egor S. Sogomonyan, Michael Gssel |
| 1996 | A diagnosability metric for parametric path delay faults. | Mukund Sivaraman, Andrzej J. Strojwas |
| 1996 | Improving the accuracy of diagnostics provided by fault dictionaries. | John W. Sheppard, William R. Simpson |
| 1996 | Self-dual parity checking-A new method for on-line testing. | Vladimir V. Saposhnikov, Alexej Dmitriev, Michael Gssel, Valerij V. Saposhnikov |
| 1996 | A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq. | Masaru Sanada |
| 1996 | Bridging fault coverage improvement by power supply control. | Michel Renovell, P. Huc, Yves Bertrand |
| 1996 | The multi-configuration: A DFT technique for analog circuits. | Michel Renovell, Florence Azas, Yves Bertrand |
| 1996 | On the effects of test compaction on defect coverage. | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
| 1996 | Increasing testability by clock transformation (getting rid of those darn states). | Krishna B. Rajan, David E. Long, Miron Abramovici |
| 1996 | Consistently dominant fault model for tristate buffer nets. | Theo J. Powell |
| 1996 | Implicit functional testing for analog circuits. | Chen-Yang Pan, Kwang-Ting Cheng |
| 1996 | Synthesis-for-scan and scan chain ordering. | Robert B. Norwood, Edward J. McCluskey |
| 1996 | A self-driven test structure for pseudorandom testing of non-scan sequential circuits. | Fidel Muradali, Janusz Rajski |
| 1996 | Analog circuit simulation and troubleshooting with FLAMES. | F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak |
| 1996 | Development of test programs in a virtual test environment. | M. Miegler, Werner Wolz |
| 1996 | Embedded two-rail checkers with on-line testing ability. | Cecilia Metra, Michele Favalli, Bruno Ricc |