| 1991 | Combining IEEE Standard 1149.1 with reduced-pin-count component test. | Steven F. Oakland |
| 1991 | Efficient test generation for built-in self-test boundary-scan template. | Prawat Nagvajara, Mark G. Karpovsky, Lev B. Levitin |
| 1991 | Circuit-level classification and testability analysis for CMOS faults. | Scott F. Midkiff, S. Wayne Bollinger |
| 1991 | IDDq benefits [digital CMOS testing]. | Steven D. McEuen |
| 1991 | Enhancement of resolution in supply current based testing for large ICs. | Yashwant K. Malaiya, Anura P. Jayasumana, Qiao Tong, Sankaran M. Menon |
| 1991 | Design for diagnosable multiple-output digital systems. | Hede Ma, Ying Liu |
| 1991 | Identification of structured automata for test evaluation. | K. El. Maadani, Jean Claude Geffroy |
| 1991 | Power-down integrated circuit built-in self-test structures. | Paul S. Levy |
| 1991 | Constraints for using IDDQ testing to detect CMOS bridging faults. | Kuen-Jong Lee, Melvin A. Breuer |
| 1991 | An approach for designing self-checking logic using residue codes. | Parag K. Lala, Fadi Y. Busaba, K. C. Yarlagadda |
| 1991 | An adaptive device impedance matching circuit. | M. C. Kohalmy |
| 1991 | Interconnect verification of multichip modules using boundary scan. | David S. Karpenske |
| 1991 | STarS: a target switching algorithm for sequential test generation. | Mark A. Heap, William A. Rogers, William B. Burns |
| 1991 | Testing of VLSI CMOS System/390 processor at card and system level. | Wilfred Hartmann, Cordt-Wilhem Starke |
| 1991 | Pseudoduplication of floating-point addition. A method of compiler generated checking of permanent hardware faults. | Wolfgang Hahn, Michael Gssel |
| 1991 | Using target faults to achieve a minimized partial scan path. | Harald Gundlach, Bernd K. Koch, Klaus D. Mller-Glaser |
| 1991 | Fault modeling and testing of self-timed circuits. | Stanford S. Guillory, Daniel G. Saab, Andrew T. Yang |
| 1991 | Test generation techniques for sequential circuits. | Nikolaus Gouders, Reinhard Kaibel |
| 1991 | At-speed testing of ASICs. | Christophe Gauthron |
| 1991 | Test pattern generation for current testable faults in static CMOS circuits. | F. Joel Ferguson, Tracy Larrabee |
| 1991 | Evaluation of detectability in BIST environment. | Sheng Feng, Yashwant K. Malaiya |
| 1991 | Linear microcircuit fault modeling and detection. | Benjamin R. Epstein, Steven R. Miller, Martin H. Czigler, David R. Gray |
| 1991 | The advantages of boundary-scan testing. | Stephen L. Dingle, Luke D. Lacroix, Peter A. Twombly |
| 1991 | Recent progress in synthesis for testability. | Srinivas Devadas, Kurt Keutzer, Abhijit Ghosh |
| 1991 | Measuring the coverage of node shorts by internal access methods. | Warren H. Debany Jr. |