| 1992 | A simulation-based approach to test pattern generation for synchronous sequential circuits. | Paolo Camurati, Fulvio Corno, Fulvio Prinetto, Matteo Sonza Reorda |
| 1992 | The roles of controllability and observability in design for test. | Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross |
| 1992 | A totally self-checking checker for a parallel unordered coding scheme. | Steven W. Burns, Niraj K. Jha |
| 1992 | An investigation of circuit partitioning for parallel test generation. | S. Wayne Bollinger, Scott F. Midkiff |
| 1992 | A mixed signal tester solution for: standards traceable AC calibration of analog modules. | Mark F. Abate |
| 1992 | On the effectiveness of simultaneous self-test techniques. | Peter A. Johnson, F. Joel Ferguson |
| 1991 | Testing the impact of process defects on ECL power-delay performance. | Jiann-Shiun Yuan, Juin J. Liou, David M. Wu |
| 1991 | Compact testing with intermediate signature analysis. | Hee Yong Youn |
| 1991 | Neural network diagnosis of IC faults. | Angus Wu, Tai-Shan Lin, C. Tseng, Jack L. Meador |
| 1991 | An optimized delay testing technique for LSSD-based VLSI logic circuits. | David M. Wu |
| 1991 | Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits. | Waisum Wong, Juin J. Liou, Jiann-Shiun Yuan, David M. Wu |
| 1991 | Delay testing and failure analysis of ECL logic with embedded memories. | Kyle G. Welch, James A. Monzel, Donald S. Kent, Donald W. Joseph |
| 1991 | High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification. | E. Weis, E. Kinsbron, G. Chanoch, M. Snyder |
| 1991 | Guardbanding VLSI EEPROM test programs. | David Sweetman |
| 1991 | A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing. | Rajagopalan Srinivasan, Charles Njinda, Melvin A. Breuer |
| 1991 | Probabilistic measures of fault equivalence in mixed-signal systems. | Mani Soma |
| 1991 | A software system architecture for testing multiple part number wafers. | Richard M. Smyczynski, Kevin Brennan |
| 1991 | VLSI procurement and qualification: NASA/GSFC experience, issues and concerns. | Ashok K. Sharma |
| 1991 | Comparison between the dynamic behavior of maximum length and cyclic shift registers. | Reda H. Seireg, Andr G. Vacroux |
| 1991 | Automated diagnosis of VLSI failures. | Paul G. Ryan, Shishpal Rawat, W. Kent Fuchs |
| 1991 | A design-for-testability expert system for silicon compilers. | R. P. van Riessen, Hans G. Kerkhoff, J. M. J. Janssen |
| 1991 | On polynomial-time testable classes of combinational circuits. | Nageswara S. V. Rao, Shunichi Toida |
| 1991 | An analysis and testing of operation induced faults in MOS VLSI. | Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya, Juney Park |
| 1991 | An analysis of feedback bridging faults in MOS VLSI. | Rochit Rajsuman |
| 1991 | Enhanced fault modeling for DRAM test and analysis. | H.-D. Oberle, M. Maue, Peter Muhmenthaler |