| 1992 | Behavior of faulty single BJT BiCMOS logic gates. | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana |
| 1992 | Redundancy removal and simplification of combinational circuits. | Prem R. Menon, Hitesh Ahuja |
| 1992 | Robust switch-level test generation. | Ben Mathew, Daniel G. Saab |
| 1992 | Techniques to increase sequential ATPG performance. | Enrico Macii, Angelo Raffaele Meo |
| 1992 | Analysis of the die test optimization algorithm for negative binomial yield statistics. | C. Mani Krishna, Adit D. Singh |
| 1992 | A concurrent checking scheme for single and multibit errors in logic circuits. | B. Kolla, Parag K. Lala, K. C. Yarlagadda |
| 1992 | On fault deletion problem in concurrent fault simulation for synchronous sequential circuits. | Kyuchull Kim, Kewal K. Saluja |
| 1992 | Built-in self-diagnostic by space-time compression of test responses. | Mark G. Karpovsky, Saeed M. Chaudhry |
| 1992 | Test pattern generation system for delay faults using a high speed simulation processor 'SP'. | Yukiko Izuta, Fumiyasu Hirose |
| 1992 | A defect-tolerant design for mask ROMs. | Kazuhiko Iwasaki, Toru Fujiwara, Tadao Kasami |
| 1992 | Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation. | Ken-ichi Imamiya, Jun-ichi Miyamoto, Nobuaki Ohtuska, Naoto Tomita, Yumiko Iyama |
| 1992 | Scan testing of latch arrays. | Michael M. Y. Hui, Benoit Nadeau-Dostie |
| 1992 | On-line testing of switched-capacitor filters. | Jos Luis Huertas, Diego Vzquez, Adoracin Rueda |
| 1992 | Simulation of physical faults in VLSI circuits. | Ibrahim N. Hajj, Terry Lee |
| 1992 | The split boundary scan register technique for testing board interconnects. | Nazar S. Haider, Nick Kanopoulos |
| 1992 | A methodology for the insertion of a hierarchical and boundary-scan compatible self test. | Oliver F. Haberl, Thomas Kropf |
| 1992 | Testability properties of acyclic structures and applications to partial scan design. | Rajesh Gupta, Melvin A. Breuer |
| 1992 | Recent advances in BIST. | Sandeep K. Gupta |
| 1992 | Design of low cost ROM based test generators. | Geetani Edirisooriya, John P. Robinson |
| 1992 | Effective concurrent test for a parallel-input multiplier using modulo 3. | Warren H. Debany Jr., Anthony R. Macera, Daniel Daskiewich, Mark Gorniak, Kevin A. Kwiat, Heather B. Dussault |
| 1992 | Empirical bounds on fault coverage loss due to LFSR aliasing. | Warren H. Debany Jr., Mark Gorniak, Daniel Daskiewich, Anthony R. Macera, Kevin A. Kwiat, Heather B. Dussault |
| 1992 | A functional BIST approach for FIR digital filters. | C. Counil, Gaston Cambon |
| 1992 | Recent advances in sequential test generation. | Kwang-Ting Cheng |
| 1992 | A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. | Manjit S. Cheema, Parag K. Lala |
| 1992 | Checksum-based concurrent error detection in linear analog systems with second and higher order stages. | Abhijit Chatterjee |