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Bernd Becker

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

209

Venues

51

Active years

1985–2023

Best venue rank

A*

Where they publish

Papers

209 indexed papers, newest first.

YearVenueTitleAuthors
2023ETSA Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernndez, Nele Mentens, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric
2023ETSAutomating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing.Nikolaos Ioannis Deligiannis, Tobias Faller, Chenghan Zhou, Riccardo Cantoro, Bernd Becker, Matteo Sonza Reorda
2023ETSConstraint-Based Automatic SBST Generation for RISC-V Processor Families.Tobias Faller, Nikolaos Ioannis Deligiannis, Markus Schwrer, Matteo Sonza Reorda, Bernd Becker
2022DATEThe Scale4Edge RISC-V Ecosystem.Wolfgang Ecker, Peer Adelt, Wolfgang Mller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jrg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz
2021DATEICP and IC3.Karsten Scheibler, Felix Winterer, Tobias Seufert, Tino Teige, Christoph Scholl, Bernd Becker
2021VTSNew Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core.Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matthias Sauer, Bernd Becker, Matteo Sonza Reorda
2021VMCAIOn Preprocessing for Weighted MaxSAT.Tobias Paxian, Pascal Raiola, Bernd Becker
2020ETSMinimal Witnesses for Security Weaknesses in Reconfigurable Scan Networks.Pascal Raiola, Tobias Paxian, Bernd Becker
2020SENSYSFIRED: A Fully-labeled hIgh-fRequency Electricity Disaggregation Dataset.Benjamin Vlker, Marc Pfeifer, Philipp M. Scholl, Bernd Becker
2020SENSYSAnnoticity: A Smart Annotation Tool and Data Browser for Electricity Datasets.Benjamin Vlker, Marc Pfeifer, Philipp M. Scholl, Bernd Becker
2019CSEDUSMILE Goes Gaming: Gamification in a Classroom Response System for Academic Teaching.Leonie Feldbusch, Felix Winterer, Johannes Gramsch, Linus Feiten, Bernd Becker
2019DATEOn Secure Data Flow in Reconfigurable Scan Networks.Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Lylina, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
2019ETSOn Integrating Lightweight Encryption in Reconfigurable Scan Networks.Benjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker, Matthias Sauer
2019FCCMActive Stereo Vision with High Resolution on an FPGA.Marc Pfeifer, Philipp M. Scholl, Rainer Voigt, Bernd Becker
2019FDTCHardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support.Mal Gay, Tobias Paxian, Devanshi Upadhyaya, Bernd Becker, Ilia Polian
2019IJCAICounterexample-Guided Strategy Improvement for POMDPs Using Recurrent Neural Networks.Steven Carr, Nils Jansen, Ralf Wimmer, Alexandru Constantin Serban, Bernd Becker, Ufuk Topcu
2019ITCSecurity Compliance Analysis of Reconfigurable Scan Networks.Natalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2018DATECharacterization of possibly detected faults by accurately computing their detection probability.Jan Burchard, Dominik Erb, Bernd Becker
2018ETSOnline prevention of security violations in reconfigurable scan networks.Ahmed Atteya, Michael A. Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
2018ETSTowards the formal verification of security properties of a Network-on-Chip router.Johanna Seplveda, Damian Aboul-Hassan, Georg Sigl, Bernd Becker, Matthias Sauer
2018IOLTSDetecting and Resolving Security Violations in Reconfigurable Scan Networks.Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodrguez Gmez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
2018UAIFinite-State Controllers of POMDPs using Parameter Synthesis.Sebastian Junges, Nils Jansen, Ralf Wimmer, Tim Quatmann, Leonore Winterer, Joost-Pieter Katoen, Bernd Becker
2018VTSEfficient generation of parametric test conditions for AMS chips with an interval constraint solver.Felix Neubauer, Jan Burchard, Pascal Raiola, Jochen Rivoir, Bernd Becker, Matthias Sauer
2018SATDynamic Polynomial Watchdog Encoding for Solving Weighted MaxSAT.Tobias Paxian, Sven Reimer, Bernd Becker
2017CADESC-square: when Satisfiability Checking and Symbolic Computation join forces.Erika brahm, John Abbott, Bernd Becker, Anna Maria Bigatti, Martin Brain, Alessandro Cimatti, James H. Davenport, Matthew England, Pascal Fontaine, Stephen Forrest, Vijay Ganesh, Alberto Griggio, Daniel Kroening, Werner M. Seiler
2017DATEFast and waveform-accurate hazard-aware SAT-based TSOF ATPG.Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker
2017DATESensitized path PUF: A lightweight embedded physical unclonable function.Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rhrmair, Ilia Polian
2017ETSBest paper.Bernd Becker, Adit D. Singh
2017ETSSpecification and verification of security in reconfigurable scan networks.Michael A. Kochte, Matthias Sauer, Laura Rodrguez Gmez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
2017FDTCAutoFault: Towards Automatic Construction of Algebraic Fault Attacks.Jan Burchard, Mael Gay, Ange-Salom Messeng Ekossono, Jan Horcek, Bernd Becker, Tobias Schubert, Martin Kreuzer, Ilia Polian
2017VLSIDAccurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model.Pascal Raiola, Dominik Erb, Sudhakar M. Reddy, Bernd Becker
2017VTSEfficient SAT-based generation of hazard-activated TSOF tests.Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
2017SATFrom DQBF to QBF by Dependency Elimination.Ralf Wimmer, Andreas Karrenbauer, Ruben Becker, Christoph Scholl, Bernd Becker
2017TACASHQSpre - An Effective Preprocessor for QBF and DQBF.Ralf Wimmer, Sven Reimer, Paolo Marin, Bernd Becker
2016ASPDACMixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2016ATVASkolem Functions for DQBF.Karina Wimmer, Ralf Wimmer, Christoph Scholl, Bernd Becker
2016CLOSERSurvey of the Cloud Computing Standards Landscape 2015.Bernd Becker, Emmanuel Darmois, Anders Kingstedt, Olivier Le Grand, Peter Schmitting, Wolfgang Ziegler
2016CLUSTERDistributed Parallel #SAT Solving.Jan Burchard, Tobias Schubert, Bernd Becker
2016DATEAccurate CEGAR-based ATPG in presence of unknown values for large industrial designs.Karsten Scheibler, Dominik Erb, Bernd Becker
2016ETSFormal verification of secure reconfigurable scan network infrastructure.Michael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2016FMCADAccurate ICP-based floating-point reasoning.Karsten Scheibler, Felix Neubauer, Ahmed Mahdi, Martin Frnzle, Tino Teige, Tom Bienmller, Detlef Fehrer, Bernd Becker
2016GIDigitale Tarnkappe: Anonymisierung in Videoaufnahmen.Sebastian Volkmann, Linus Feiten, Christian Zimmermann, Sebastian Sester, Laura Wehle, Bernd Becker
2016VTSEffective generation and evaluation of diagnostic SBST programs.Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2016SATDependency Schemes for DQBF.Ralf Wimmer, Christoph Scholl, Karina Wimmer, Bernd Becker
2016SYNASCAccurate Dead Code Detection in Embedded C Code by Arithmetic Constraint Solving.Felix Neubauer, Karsten Scheibler, Bernd Becker, Ahmed Mahdi, Martin Frnzle, Tino Teige, Tom Bienmller, Detlef Fehrer
2015DATESolving DQBF through quantifier elimination.Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker
2015DATEOn the automatic generation of SBST test programs for in-field test.Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker
2015ETSImproving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases.Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
2015ETSIdentification of high power consuming areas with gate type and logic level information.Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2015ETSImproving test pattern generation in presence of unknown values beyond restricted symbolic logic.Karsten Scheibler, Dominik Erb, Bernd Becker
2015FMCounterexamples for Expected Rewards.Tim Quatmann, Nils Jansen, Christian Dehnert, Ralf Wimmer, Erika brahm, Joost-Pieter Katoen, Bernd Becker
2015VTSMulti-cycle Circuit Parameter Independent ATPG for interconnect open defects.Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2015VTSImproving diagnosis resolution of a fault detection test set.Andreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
2015SATLaissez-Faire Caching for Parallel #SAT Solving.Jan Burchard, Tobias Schubert, Bernd Becker
2015SATPreprocessing for DQBF.Ralf Wimmer, Karina Gitina, Jennifer Nist, Christoph Scholl, Bernd Becker
2015SETTACost vs. Time in Stochastic Games and Markov Automata.Hassan Hatefi, Bettina Braitling, Ralf Wimmer, Luis Mara Ferrer Fioriti, Holger Hermanns, Bernd Becker
2015VMCAIAbstraction-Based Computation of Reward Measures for Markov Automata.Bettina Braitling, Luis Mara Ferrer Fioriti, Hassan Hatefi, Ralf Wimmer, Bernd Becker, Holger Hermanns
2014ATVAIncremental Encoding and Solving of Cardinality Constraints.Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
2014DATEEfficient SMT-based ATPG for interconnect open defects.Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker
2014DATEUsing MaxBMC for Pareto-optimal circuit initialization.Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker
2014DATEAn effective approach to automatic functional processor test generation for small-delay faults.Andreas Riefert, Lyl M. Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker
2014ETSVariation-aware deterministic ATPG.Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
2014FMCADUsing interval constraint propagation for pseudo-Boolean constraint solving.Karsten Scheibler, Bernd Becker
2014ITCTest pattern generation in presence of unknown values based on restricted symbolic logic.Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2014VLSIDSAT-Based Test Pattern Generation with Improved Dynamic Compaction.Alexander Czutro, Sudhakar M. Reddy, Ilia Polian, Bernd Becker
2014VLSIDEfficient SAT-Based Circuit Initialization for Larger Designs.Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker
2013ASPDACProvably optimal test cube generation using quantified boolean formula solving.Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker
2013CADEA Symbiosis of Interval Constraint Propagation and Cylindrical Algebraic Decomposition.Ulrich Loup, Karsten Scheibler, Florian Corzilius, Erika brahm, Bernd Becker
2013DATEAccurate QBF-based test pattern generation in presence of unknown values.Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker
2013DATEEfficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker
2013GISMILE: Smartphones in der Lehre - ein Rck- und berblick.Linus Feiten, Katrin Weber, Bernd Becker
2013ICCDEquivalence checking of partial designs using dependency quantified Boolean formulae.Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker
2013ITCEarly-life-failure detection using SAT-based ATPG.Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker
2013LPNMRAccurate Computation of Sensitizable Paths Using Answer Set Programming.Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub
2013VTSIdentification of critical variables using an FPGA-based fault injection framework.Andreas Riefert, Jrg Mller, Matthias Sauer, Wolfram Burgard, Bernd Becker
2012ATVAALLQBF Solving by Computational Learning.Bernd Becker, Rdiger Ehlers, Matthew Lewis, Paolo Marin
2012ATVAThe COMICS Tool - Computing Minimal Counterexamples for DTMCs.Nils Jansen, Erika brahm, Matthias Volk, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
2012CSEDUSMILE - Smartphones in Lectures - Initiating a Smartphone-based Audience Response System as a Student Project.Linus Feiten, Manuel Bhrer, Sebastian Sester, Bernd Becker
2012DATEOn the optimality of K longest path generation algorithm under memory constraints.Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
2012DATEVerification of partial designs using incremental QBF solving.Paolo Marin, Christian Miller, Matthew Lewis, Bernd Becker
2012ETSMulti-conditional SAT-ATPG for power-droop testing.Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker
2012ETSExact stuck-at fault classification in presence of unknowns.Stefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker
2012ETSOn the quality of test vectors for post-silicon characterization.Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian
2012ICCADSmall-delay-fault ATPG with waveform accuracy.Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker
2012ITCFunctional test of small-delay faults using SAT and Craig interpolation.Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker
2012VLSIDAnalysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker
2012VTSSAT-ATPG using preferences for improved detection of complex defect mechanisms.Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker
2012SATIncremental QBF Preprocessing for Partial Design Verification - (Poster Presentation).Paolo Marin, Christian Miller, Bernd Becker
2012TACASMinimal Critical Subsystems for Discrete-Time Markov Models.Ralf Wimmer, Nils Jansen, Erika brahm, Bernd Becker, Joost-Pieter Katoen
2011ASPDACFault diagnosis aware ATE assisted test response compaction.J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2011ATVAHierarchical Counterexamples for Discrete-Time Markov Chains.Nils Jansen, Erika brahm, Jens Katelaan, Ralf Wimmer, Joost-Pieter Katoen, Bernd Becker
2011COCOAIntegration of an LP Solver into Interval Constraint Propagation.Ernst Althaus, Bernd Becker, Daniel Dumitriu, Stefan Kupferschmid
2011DATEHyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing.Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker
2011DATEIntegration of orthogonal QBF solving techniques.Sven Reimer, Florian Pigorsch, Christoph Scholl, Bernd Becker
2011DDECSProof certificates and non-linear arithmetic constraints.Stefan Kupferschmid, Bernd Becker, Tino Teige, Martin Frnzle
2011DDECSSAT-based analysis of sensitisable paths.Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker
2011ETSTowards Variation-Aware Test Methods.Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell
2011FORTECounterexample Generation for Markov Chains Using SMT-Based Bounded Model Checking.Bettina Braitling, Ralf Wimmer, Bernd Becker, Nils Jansen, Erika brahm
2011IOLTSEstimation of component criticality in early design steps.Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker
2011IOLTSAn FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.Matthias Sauer, Victor Tomashevich, Jrg Mller, Matthew Lewis, Andreas Spilla, Ilia Polian, Bernd Becker, Wolfram Burgard
2011MEMOCODEReachability analysis for incomplete networks of Markov decision processes.Ralf Wimmer, Ernst Moritz Hahn, Holger Hermanns, Bernd Becker
2010DSNMassive statistical process variations: A grand challenge for testing nanoelectronic circuits.Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
2010SATEncoding Techniques, Craig Interpolants and Bounded Model Checking for Incomplete Designs.Christian Miller, Stefan Kupferschmid, Matthew Lewis, Bernd Becker
2009IOLTSATPG-based grading of strong fault-secureness.Marc Hunger, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, Bernd Becker
2009PDPTAPicoso - A Parallel Interval Constraint Solver.Natalia Kalinnik, Tobias Schubert, Erika brahm, Ralf Wimmer, Bernd Becker
2009VLSIDTIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
2009VTSAn Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker
2009SATPaQuBE: Distributed QBF Solving with Advanced Knowledge Sharing.Matthew Lewis, Paolo Marin, Tobias Schubert, Massimo Narizzano, Bernd Becker, Enrico Giunchiglia
2009SSSDependability Engineering of Silent Self-stabilizing Systems.Abhishek Dhama, Oliver E. Theel, Pepijn Crouzen, Holger Hermanns, Ralf Wimmer, Bernd Becker
2009VMCAICounterexample Generation for Discrete-Time Markov Chains Using Bounded Model Checking.Ralf Wimmer, Bettina Braitling, Bernd Becker
2008DATEResistive Bridging Fault Simulation of Industrial Circuits.Piet Engelke, Ilia Polian, Jrgen Schlffel, Bernd Becker
2008DDECSDiagnosis of Realistic Defects Based on the X-Fault Model.Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
2008DDECSProbabilistic Model Checking and Reliability of Results.Ralf Wimmer, Alexander Kortus, Marc Herbstritt, Bernd Becker
2008DSNA study of cognitive resilience in a JPEG compressor.Damian Nowroth, Ilia Polian, Bernd Becker
2008ETSA Simulator of Small-Delay Faults Caused by Resistive-Open Defects.Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
2008ETSSelective Hardening in Early Design Steps.Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
2008ICCDPropositional approximations for bounded model checking of partial circuit designs.Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer
2008ITCExtraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2008VTSAutomatic Test Pattern Generation for Interconnect Open Defects.Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng
2007ASPDACMultithreaded SAT Solving.Matthew Lewis, Tobias Schubert, Bernd Becker
2007CAVLIRA: Handling Constraints of Linear Arithmetics over the Integers and the Reals.Bernd Becker, Christian Dax, Jochen Eisinger, Felix Klaedtke
2007DDECSOn Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata.Marc Herbstritt, Bernd Becker, Erika brahm, Christian Herde
2007ICCADComputation of minimal counterexamples by using black box techniques and symbolic methods.Tobias Nopper, Christoph Scholl, Bernd Becker
2007IOLTSIdentification of Critical Errors in Imaging Applications.Ilia Polian, Damian Nowroth, Bernd Becker
2007VTSAn Analysis Framework for Transient-Error Tolerance.John P. Hayes, Ilia Polian, Bernd Becker
2006ATVASigref- A Symbolic Bisimulation Tool Box.Ralf Wimmer, Marc Herbstritt, Holger Hermanns, Kelley Strampp, Bernd Becker
2006DDECSAutomatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
2006DDECSMinimization of Large State Spaces using Symbolic Branching Bisimulation.Ralf Wimmer, Marc Herbstritt, Bernd Becker
2006FMICSParallel SAT Solving in Bounded Model Checking.Erika brahm, Tobias Schubert, Bernd Becker, Martin Frnzle, Christian Herde
2006ICCDPower Droop Testing.Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
2005DATEEvolutionary Optimization in Code-Based Test Compression.Ilia Polian, Alejandro Czutro, Bernd Becker
2005ETSA unified fault model and test generation procedure for interconnect opens and bridges.Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker
2005ITCTransient fault characterization in dynamic noisy environments.Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
2005PDPTAKnowledge Sharing in a Microcontroller based Parallel SAT Solver.Tobias Schubert, Bernd Becker
2005PERCOMSecuring Wireless Networks in a University Environment.Jochen Eisinger, Peter Winterer, Bernd Becker
2005VLSIDOrthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.Thomas Eschbach, Wolfgang Gnther, Bernd Becker
2005VTSResistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.Ilia Polian, Sandip Kundu, Jean-Marc Gallire, Piet Engelke, Michel Renovell, Bernd Becker
2005SATSpeedup Techniques Utilized in Modern SAT Solvers.Matthew D. T. Lewis, Tobias Schubert, Bernd Becker
2005VMCAIOptimizing Bounded Model Checking for Linear Hybrid Systems.Erika brahm, Bernd Becker, Felix Klaedtke, Martin Steffen
2004ETSAutomatic test pattern generation for resistive bridging faults.Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2004ISCASPlacement and routing optimization for circuits derived from BDDs.Thomas Eschbach, Rolf Drechsler, Bernd Becker
2004ITCX-Masking During Logic BIST and Its Impact on Defect Coverage.Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
2004VTSThe Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
2004SATEarly Conflict Detection Based BCP for SAT Solving.Matthew D. T. Lewis, Tobias Schubert, Bernd Becker
2003DATEEvolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.Ilia Polian, Bernd Becker, Sudhakar M. Reddy
2003ETSModeling feedback bridging faults with non-zero resistance.Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
2003ITCSimulating Resistive Bridging and Stuck-At Faults.Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2003SATConflict-Based Selection of Branching Rules.Marc Herbstritt, Bernd Becker
2002ETSSimulating realistic bridging and crosstalk faults in an industrial setting.Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker
2002GDCrossing Reduction by Windows Optimization.Thomas Eschbach, Wolfgang Gnther, Rolf Drechsler, Bernd Becker
2002ICCDChecking Equivalence for Circuits Containing Incompletely Specified Boxes.Christoph Scholl, Bernd Becker
2002IOLTSStop & Go BIST.Ilia Polian, Bernd Becker
2002IOLTSSequential n -Detection Criteria: Keep It Simple.Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker
2001ASPDACApplication of linearly transformed BDDs in sequential verification.Wolfgang Gnther, Andreas Hett, Bernd Becker
2001ASPDACThe multiple variable order problem for binary decision diagrams: theory and practical application.Christoph Scholl, Bernd Becker, Andreas Brogle
2001DACChecking Equivalence for Partial Implementations.Christoph Scholl, Bernd Becker
2001DSDGreedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Gnther
2001EMOMulti-objective Optimisation Based on RelationNicole Drechsler, Rolf Drechsler, Bernd Becker
2001ISCASExploiting don't cares to minimize *BMDs.Christoph Scholl, Marc Herbstritt, Bernd Becker
2001VTSMultiple Scan Chain Design for Two-Pattern Testing.Ilia Polian, Bernd Becker
2000DACDistance driven finite state machine traversal.Andreas Hett, Christoph Scholl, Bernd Becker
2000DATEOn the Generation of Multiplexer Circuits for Pass Transistor Logic.Christoph Scholl, Bernd Becker
2000ETSA parameterizable fault simulator for bridging faults.Piet Engelke, Bernd Becker, Martin Keim
2000GDUntitled recordWolfgang Gnther, Robby Schnfeld, Bernd Becker, Paul Molitor
2000GECCOSpecialized Hardware for Implementation of Evolutionary Algorithms.Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker
2000ICCDMinimization of Ordered Pseudo Kronecker Decision Diagrams.Per Lindgren, Rolf Drechsler, Bernd Becker
1999ASPDACCombining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.Martin Keim, Nicole Drechsler, Bernd Becker
1999ETSA scalable BIST architecture for delay faults.Martin Keim, Ilia Polian, Harry Hengster, Bernd Becker
1999ICCDSynthesis of Pseudo Kronecker Lattice Diagrams.Per Lindgren, Rolf Drechsler, Bernd Becker
1999ISCASGrouping heuristics for word-level decision diagrams.Rolf Drechsler, Marc Herbstritt, Bernd Becker
1999ISCASExact channel routing using symbolic representation.Frank Schmiedle, Rolf Drechsler, Bernd Becker
1998ICCADWord-level decision diagrams, WLCDs and division.Christoph Scholl, Bernd Becker, Thomas M. Weis
1997ASPDACOn the representational power of bit-level and word-level decision diagrams.Bernd Becker, Rolf Drechsler, Reinhard Enders
1997ASPDACLearning heuristics for OKFDD minimization by evolutionary algorithms.Nicole Gckel, Rolf Drechsler, Bernd Becker
1997DATETestability of 2-level AND/EXOR circuits.Rolf Drechsler, Harry Hengster, Horst Schfer, Joachim Hartmann, Bernd Becker
1997DATEFast and efficient construction of BDDs by reordering based synthesis.Andreas Hett, Rolf Drechsler, Bernd Becker
1997ICCADFunctional simulation using binary decision diagrams.Christoph Scholl, Rolf Drechsler, Bernd Becker
1997VLSIDDecision Diagrams in Synthesis - Algorithms, Applications and Extensions.Bernd Becker, Rolf Drechsler
1997VLSID(Quasi-) Linear Path Delay Fault Tests for Adders.Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy
1997VTSPolynomial Formal Verification of Multipliers.Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
1997VTSOn Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms.Can kmen, Martin Keim, Rolf Krieger, Bernd Becker
1997TACASManipulation Algorithms for K*BMDs.Rolf Drechsler, Bernd Becker, Stefan Ruppertz
1996DATEA Fast Optimal Robust Path Delay Fault Testable Adder.Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy
1996DATEK*BMDs: A New Data Structure for Verification.Rolf Drechsler, Bernd Becker, Stefan Ruppertz
1996ITCLocal Transformations and Robust Dependent Path Delay.Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy
1996PPSNLearning Heuristics for OBDD Minimization by Evolutionary Algorithms.Rolf Drechsler, Nicole Gckel, Bernd Becker
1996VTSOn the (non-)resetability of synchronous sequential circuits.Martin Keim, Bernd Becker, Birgitta Stenner
1995ASPDACLearning heuristics by genetic algorithms.Rolf Drechsler, Bernd Becker
1995DACSymbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy.Rolf Krieger, Bernd Becker, Martin Keim
1995DATEHow many decomposition types do we need? [decision diagrams].Bernd Becker, Rolf Drechsler
1995DATESynthesis for testability: circuits derived from ordered Kronecker functional decision diagrams.Bernd Becker, Rolf Drechsler
1995DATESympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.Rolf Drechsler, Bernd Becker
1995ICALPOKFDDs versus OBDDs and OFDDs.Bernd Becker, Rolf Drechsler, Michael Theobald
1995ICCDDynamic minimization of OKFDDs.Rolf Drechsler, Bernd Becker
1995LATINOn the Relation Betwen BDDs and FDDs.Bernd Becker, Rolf Drechsler, Ralph Werchner
1995VTSOn the application of local circuit transformations with special emphasis on path delay fault testability.Harry Hengster, Rolf Drechsler, Bernd Becker
1994DACEfficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski
1994ICCDOFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms.Bernd Becker, Rolf Drechsler
1994ITCA Hybrid Fault Simulator for Synchronous Sequential Circuits.Rolf Krieger, Bernd Becker, Martin Keim
1994VLSIDTestability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model.Harry Hengster, Rolf Drechsler, Bernd Becker
1993VLSIDFAST-SC: Fast Fault Simulation in Synchronous Sequential Circuits.Bernd Becker, Rolf Krieger
1992MFCSSome Remarks on the Test Complexity of Iterative Logic Arrays.Bernd Becker, Joachim Hartmann
1992STACSSynthesis for Testability: Binary Decision Diagrams.Bernd Becker
1990SPAAOptimal-Time Multipliers and C-Testability.Bernd Becker, Joachim Hartmann
1988STACSOn the Construction of Optimal Time Adders (Extended Abstract).Bernd Becker, Reiner Kolla
1987DACHierarchical Design Based on a Calculus of Nets.Bernd Becker, Gnter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof
1986FOCSHow Robust Is the n-Cube? (Extended Abstract)Bernd Becker, Hans Ulrich Simon
1986MFCSEfficient Testing of Optimal Time Adders (Extended Abstract).Bernd Becker
1985STACSLayouts with Wires of Balanced Length.Bernd Becker, Hans-Georg Osthof