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David T. Blaauw

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

198

Venues

21

Active years

1988–2026

Best venue rank

A*

Where they publish

Papers

198 indexed papers, newest first.

YearVenueTitleAuthors
2026HPDCAccelerating Block Low-Rank Foundation Model Inference on Memory-Constrained GPUs.Pierre Abillama, Changwoo Lee, Juechu Dong, David T. Blaauw, Dennis Sylvester, Hun-Seok Kim
2024ISLPEDParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications.Seungkyu Choi, Huanshihong Deng, Kuan-Yu Chen, Yufan Yue, David T. Blaauw, Hun-Seok Kim
2023ISCATaskFusion: An Efficient Transfer Learning Architecture with Dual Delta Sparsity for Multi-Task Natural Language Processing.Zichen Fan, Qirui Zhang, Pierre Abillama, Sara Shoouri, Changwoo Lee, David T. Blaauw, Hun-Seok Kim, Dennis Sylvester
2023ISCAGenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2023SENSYSGlobal Localization of Energy-Constrained Miniature RF Emitters using Low Earth Orbit Satellites.Yunfan Wang, Steve Young, Demba Komma, Jaechan Lim, Zhen Feng, Zichen Fan, Chien-Wei Tseng, Hun-Seok Kim, David T. Blaauw
2022ICMLVariational Mixtures of ODEs for Inferring Cellular Gene Expression Dynamics.Yichen Gu, David T. Blaauw, Joshua D. Welch
2022ISCAMeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows.Siying Feng, Xin He, Kuan-Yu Chen, Liu Ke, Xuan Zhang, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2022ISCANDMiner: accelerating graph pattern mining using near data processing.Nishil Talati, Haojie Ye, Yichen Yang, Leul Belayneh, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2022ISCASEnabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor.Daniel W. Bliss, Tutu Ajayi, Ali Akoglu, Ilkin Aliyev, Toygun Basaklar, Leul Belayneh, David T. Blaauw, John S. Brunhaver, Chaitali Chakrabarti, Liangliang Chang, Kuan-Yu Chen, Ming-Hung Chen, Xing Chen, Alex R. Chiriyath, Alhad Daftardar, Ronald G. Dreslinski, Arindam Dutta, Allen-Jasmin Farcas, Yukang Fu, A. Alper Goksoy, Xin He, Md Sahil Hassan, Andrew Herschfelt, Jacob Holtom, Hun-Seok Kim, A. N. Krishnakumar, Yang Li, Owen Ma, Joshua Mack, Saurav Mallik, Sumit K. Mandal, Radu Marculescu, Brittany M. McCall, Trevor N. Mudge, mit Y. Ogras, Vishrut Pandey, Saquib Ahmad Siddiqui, Yu-Hsiu Sun, Adarsh A. Venkataramani, Xiangdong Wei, B. R. Willis, Hanguang Yu, Yufan Yue
2022ISCASImproving Energy Efficiency of Convolutional Neural Networks on Multi-core Architectures through Run-time Reconfiguration.Yan Xiong, Jingtao Li, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2022ISLPEDA Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding.Yufan Yue, Tutu Ajayi, Xueyang Liu, Peiwen Xing, Zihan Wang, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim
2022MICROMint: An Accelerator For Mining Temporal Motifs.Nishil Talati, Haojie Ye, Sanketh Vedula, Kuan-Yu Chen, Yuhan Chen, Daniel Liu, Yichao Yuan, David T. Blaauw, Alex M. Bronstein, Trevor N. Mudge, Ronald G. Dreslinski
2021ISCAAccelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees.Arun Subramaniyan, Jack Wadden, Kush Goliya, Nathan Ozog, Xiao Wu, Satish Narayanasamy, David T. Blaauw, Reetuparna Das
2021ISPASSGenomicsBench: A Benchmark Suite for Genomics.Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2021MICROSquiggleFilter: An Accelerator for Portable Virus Detection.Timothy Dunn, Harisankar Sadasivan, Jack Wadden, Kush Goliya, Kuan-Yu Chen, David T. Blaauw, Reetuparna Das, Satish Narayanasamy
2021MOBICOMmSAIL: milligram-scale multi-modal sensor platform for monarch butterfly migration tracking.Inhee Lee, Roger Hsiao, Gordy Carichner, Chin-Wei Hsu, Mingyu Yang, Sara Shoouri, Katherine Ernst, Tess Carichner, Yuyang Li, Jaechan Lim, Cole R. Julick, Eunseong Moon, Yi Sun, Jamie Phillips, Kristi L. Montooth, Delbert A. Green II, Hun-Seok Kim, David T. Blaauw
2020ICASSPAccelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture.A. Soorishetty, Jian Zhou, Subhankar Pal, David T. Blaauw, H. Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2020ISCASAccelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture.Yan Xiong, Jian Zhou, Subhankar Pal, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti
2020MICROSeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space.Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2019DATEIoTSechang Oh, Minchang Cho, Xiao Wu, Yejoong Kim, Li-Xuan Chuo, Wootaek Lim, Pat Pannuto, Suyoung Bang, Kaiyuan Yang, Hun-Seok Kim, Dennis Sylvester, David T. Blaauw
2018ASPDACA 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries.Junwon Jeong, Seokhyeon Jeong, Chulwoo Kim, Dennis Sylvester, David T. Blaauw
2018ASPDACEdge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC.Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung
2018HPCAOuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2018ISCANeural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks.Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi R. Iyer, Dennis Sylvester, David T. Blaauw, Reetuparna Das
2018ISCAGenAx: A Genome Sequencing Accelerator.Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy
2017HPCACompute Caches.Shaizeen Aga, Supreet Jeloka, Arun Subramaniyan, Satish Narayanasamy, David T. Blaauw, Reetuparna Das
2017ISCAA Programmable Galois Field Processor for the Internet of Things.Yajing Chen, Shengshuo Lu, Cheng Fu, David T. Blaauw, Ronald Dreslinski Jr., Trevor N. Mudge, Hun-Seok Kim
2017ISCASRectified-linear and recurrent neural networks built with spin devices.Qing Dong, Kaiyuan Yang, Laura Fick, David T. Blaauw, Dennis Sylvester
2017MICROCache automaton.Arun Subramaniyan, Jingcheng Wang, Ezhil R. M. Balasubramanian, David T. Blaauw, Dennis Sylvester, Reetuparna Das
2017MOBICOMRF-Echo: A Non-Line-of-Sight Indoor Localization System Using a Low-Power Active RF Reflector ASIC Tag.Li-Xuan Chuo, Zhihong Luo, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim
2016DACNear-threshold computing in FinFET technologies: opportunities for improved voltage scalability.Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2016HPCAA low power software-defined-radio baseband processor for the Internet of Things.Yajing Chen, Shengshuo Lu, Hun-Seok Kim, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2016ICIPLow complexity optical flow using neighbor-guided semi-global matching.Jiang Xiang, Ziyun Li, David T. Blaauw, Hun-Seok Kim, Chaitali Chakrabarti
2015ISCAMBus: an ultra-low power interconnect bus for next generation nanopower systems.Pat Pannuto, Yoonmyung Lee, Ye-Sheng Kuo, Zhiyoong Foo, Benjamin P. Kempke, Gyouho Kim, Ronald G. Dreslinski, David T. Blaauw, Prabal Dutta
2015ISCASRacetrack converter: A low power and compact data converter using racetrack spintronic devices.Qing Dong, Kaiyuan Yang, Laura Fick, David Fick, David T. Blaauw, Dennis Sylvester
2014DACQuality-of-Service for a High-Radix Switch.Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David T. Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge
2014DACVIX: Virtual Input Crossbar for Efficient Switch Allocation.Supriya Rao, Supreet Jeloka, Reetuparna Das, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2014ISCASChip-on-mud: Ultra-low power ARM-based oceanic sensing system powered by small-scale benthic microbial fuel cells.Gyouho Kim, Adriane Wolfe, Richard Bell, Suyoung Bang, Yoonmyung Lee, Inhee Lee, Yejoong Kim, Lewis Hsu, Jeffrey Kagan, Meriah Arias-Thode, Bart Chadwick, Dennis Sylvester, David T. Blaauw
2014ISLPEDEnergy-efficient dot product computation using a switched analog circuit architecture.Ihab Nahlus, Eric P. Kim, Naresh R. Shanbhag, David T. Blaauw
2014MICROHi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration.Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw
2013HPCAScaling towards kilo-core processors with asymmetric high-radix topologies.Nilmini Abeyratne, Reetuparna Das, Qingkun Li, Korey Sewell, Bharan Giridhar, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge
2013ICASSPA low-power VGA full-frame feature extraction processor.Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
2013ISCASA fully integrated switched-capacitor based PMU with adaptive energy harvesting technique for ultra-low power sensing applications.Suyoung Bang, Yoonmyung Lee, Inhee Lee, Yejoong Kim, Gyouho Kim, David T. Blaauw, Dennis Sylvester
2013SCExploring DRAM organizations for energy-efficient and resilient exascale memories.Bharan Giridhar, Michael Cieslak, Deepankar Duggal, Ronald G. Dreslinski, Hsing Min Chen, Robert Patti, Betina Hold, Chaitali Chakrabarti, Trevor N. Mudge, David T. Blaauw
2013SENSYSM3: a mm-scale wireless energy harvesting sensor platform.Pat Pannuto, Yoonmyung Lee, Zhiyoong Foo, David T. Blaauw, Prabal Dutta
2012ACSSCCircuits for ultra-low power millimeter-scale sensor nodes.Yoonmyung Lee, Dennis Sylvester, David T. Blaauw
2012DACCircuit and system design guidelines for ultra-low power sensor nodes.Yoonmyung Lee, Yejoong Kim, Dongmin Yoon, David T. Blaauw, Dennis Sylvester
2012DACAssessing the performance limits of parallelized near-threshold computing.Nathaniel Ross Pinckney, Korey Sewell, Ronald G. Dreslinski, David Fick, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2012DACHigh radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service.Sudhir Satpathy, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw
2012DACProcess variation in near-threshold wide SIMD architectures.Sangwon Seo, Ronald G. Dreslinski, Mark Woh, Yongjun Park, Chaitali Chakrabarti, Scott A. Mahlke, David T. Blaauw, Trevor N. Mudge
2012ISLPEDAn adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs.Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David T. Blaauw, Dennis Sylvester
2011DACPipeline strategy for improving optimal energy efficiency in ultra-low voltage design.Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester
2011DATEA confidence-driven model for error-resilient computing.Chia-Hsiang Chen, Yejoong Kim, Zhengya Zhang, David T. Blaauw, Dennis Sylvester, Helia Naeimi, Sumeet Sandhu
2011DATELow power interconnects for SIMD computers.Mark Woh, Sudhir Satpathy, Ronald G. Dreslinski, Danny Kershaw, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge
2011ICASSPEnergy-optimized high performance FFT processor.Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester
2011ISCASA dense 45nm half-differential SRAM with lower minimum operating voltage.Gregory K. Chen, Michael Wieckowski, Daeyeon Kim, David T. Blaauw, Dennis Sylvester
2011ISCASA 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme.Daeyeon Kim, Gregory K. Chen, Matthew Fojtik, Mingoo Seok, David T. Blaauw, Dennis Sylvester
2011ISLPEDVariation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs.Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David T. Blaauw, Dennis Sylvester
2010ASPDACAnalyzing electrical effects of RTA-driven local anneal temperature variation.Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David T. Blaauw
2010ASPDACDesign time body bias selection for parametric yield improvement.Cheng Zhuo, Yung-Hsu Chang, Dennis Sylvester, David T. Blaauw
2010DACClosed-form modeling of layout-dependent mechanical stress.Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw
2010DACEfficient smart monte carlo based SSTA on graphics processing units with improved resource utilization.Vineeth Veetil, Yung-Hsu Chang, Dennis Sylvester, David T. Blaauw
2010DATEA black box method for stability analysis of arbitrary SRAM cell structures.Michael Wieckowski, Dennis Sylvester, David T. Blaauw, Vikas Chandra, Sachin Idgunji, Cezary Pietrzyk, Robert C. Aitken
2010DATEProcess variation and temperature-aware reliability management.Cheng Zhuo, Dennis Sylvester, David T. Blaauw
2010ICCADAnalysis and optimization of SRAM robustness for double patterning lithography.Vivek Joshi, Kanak Agarwal, David T. Blaauw, Dennis Sylvester
2010ICCADA lower bound computation method for evaluation of statistical design techniques.Vineeth Veetil, Dennis Sylvester, David T. Blaauw
2010ICCADActive learning framework for post-silicon variation extraction and test cost reduction.Cheng Zhuo, Kanak Agarwal, David T. Blaauw, Dennis Sylvester
2010ISCASCircuit design advances to enable ubiquitous sensing environments.Mingoo Seok, Scott Hanson, Michael Wieckowski, Gregory K. Chen, Yu-Shiang Lin, David T. Blaauw, Dennis Sylvester
2010ISLPEDClock network design for ultra-low power applications.Mingoo Seok, David T. Blaauw, Dennis Sylvester
2009DACAddressing design margins through error-tolerant circuits.Shidhartha Das, David T. Blaauw, David M. Bull, Krisztin Flautner, Rob Aitken
2009DACVicis: a reliable network for unreliable silicon.David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacco, David T. Blaauw, Dennis Sylvester
2009DACWorst-case aggressor-victim alignment with current-source driver models.Ravikishore Gandikota, Li Ding, Peivand Tehrani, David T. Blaauw
2009DACEfficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.Vineeth Veetil, Dennis Sylvester, David T. Blaauw, Saumil Shah, Steffen Rochel
2009DATEA highly resilient routing algorithm for fault-tolerant NoCs.David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David T. Blaauw
2009ICCADPost-fabrication measurement-driven oxide breakdown reliability prediction and management.Cheng Zhuo, David T. Blaauw, Dennis Sylvester
2009ICCDInterconnect performance corners considering crosstalk noise.Ravikishore Gandikota, David T. Blaauw, Dennis Sylvester
2009ISCASAdaptive Design for Nanometer Technology.Shidhartha Das, David T. Blaauw
2009ISLPEDLow power circuit design based on heterojunction tunneling transistors (HETTs).Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, Dennis Sylvester, David T. Blaauw
2008ACSSCOptimizing addition for sub-threshold logic.David T. Blaauw, James Kitchener, Braden Phillips
2008DACModeling crosstalk in statistical static timing analysis.Ravikishore Gandikota, David T. Blaauw, Dennis Sylvester
2008DACLeakage power reduction using stress-enhanced layouts.Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal
2008DACEfficient Monte Carlo based incremental statistical timing analysis.Vineeth Veetil, Dennis Sylvester, David T. Blaauw
2008DATETransistor-Specific Delay Modeling for SSTA.Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran
2008ICCADA statistical approach for full-chip gate-oxide reliability analysis.Kaviraj Chopra, Cheng Zhuo, David T. Blaauw, Dennis Sylvester
2008ICCADSTEEL: a technique for stress-enhanced standard cell library design.Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw
2008ICCADOn the decreasing significance of large standard cells in technology mapping.Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David T. Blaauw
2008ISCASLow-voltage circuit design for widespread sensing applications.Yu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall D. Wise, Ann Marie Sastry, David T. Blaauw, Dennis Sylvester
2008ISLPEDOptimal technology selection for minimizing energy and variability in low voltage applications.Mingoo Seok, Dennis Sylvester, David T. Blaauw
2008ISLPEDVariation-aware gate sizing and clustering for post-silicon optimized circuits.Cheng Zhuo, David T. Blaauw, Dennis Sylvester
2008MICROReconfigurable energy efficient near threshold cache architectures.Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztin Flautner
2007ASPDACTiming-Aware Decoupling Capacitance Allocation in Power Distribution Networks.Sanjay Pant, David T. Blaauw
2007DACTop-k Aggressors Sets in Delay Noise Analysis.Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer
2007DACNanometer Device Scaling in Subthreshold Circuits.Scott Hanson, Mingoo Seok, Dennis Sylvester, David T. Blaauw
2007DACAnalysis and Optimization of Sleep Modes in Subthreshold Circuit Design.Mingoo Seok, Scott Hanson, Dennis Sylvester, David T. Blaauw
2007ICCADYield-driven near-threshold SRAM design.Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim
2007ICCADVictim alignment in crosstalk aware timing analysis.Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada
2007ICCADSoft-edge flip-flops for improved timing yield: design and optimization.Vivek Joshi, David T. Blaauw, Dennis Sylvester
2007ISLPEDA robust edge encoding technique for energy-efficient multi-cycle interconnect.Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy
2007ISLPEDEnergy efficient near-threshold chip multi-processing.Bo Zhai, Ronald G. Dreslinski, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester
2006DACReliability modeling and management in dynamic microprocessor-based systems.Eric Karl, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge
2006DATEAn efficient static algorithm for computing the soft error rates of combinational circuits.Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester
2006ICCADA new statistical max operation for propagating skewness in statistical timing analysis.Kaviraj Chopra, Bo Zhai, David T. Blaauw, Dennis Sylvester
2006ICCADAnalysis and modeling of CD variation for statistical static timing.Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao
2006ICCADA statistical framework for post-silicon tuning through body bias clustering.Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw
2006ICCADSoft error reduction in combinational logic using gate resizing and flipflop selection.Rajeev R. Rao, David T. Blaauw, Dennis Sylvester
2006ICCDAn Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks.Sanjay Pant, David T. Blaauw
2006ISCASEnergy efficient design for subthreshold supply voltage operation.David T. Blaauw, Bo Zhai
2006ISLPEDA new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits.Scott Hanson, Dennis Sylvester, David T. Blaauw
2006ISLPEDEnergy optimality and variability in subthreshold design.Scott Hanson, Bo Zhai, David T. Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang
2005ASPDACStatistical modeling of cross-coupling effects in VLSI interconnects.Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David T. Blaauw
2005ASPDACAchieving continuous VKanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan
2005ASPDACOpportunities and challenges for better than worst-case design.Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge
2005ASPDACLeakage power: trends, analysis and avoidance.David T. Blaauw, Anirudh Devgan, Farid N. Najm
2005ASPDACRuntime leakage minimization through probability-aware dual-Vt or dual-tox assignment.Dongwoo Lee, David T. Blaauw, Dennis Sylvester
2005CASESA second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw
2005DACCircuit optimization using statistical static timing analysis.Aseem Agarwal, Kaviraj Chopra, David T. Blaauw, Vladimir Zolotov
2005DACCAD tools for variation tolerance.David T. Blaauw, Kaviraj Chopra
2005DACAccurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director
2005DATEStatistical Timing Based Optimization using Gate Sizing.Aseem Agarwal, Kaviraj Chopra, David T. Blaauw
2005DATEDVS for On-Chip Bus Designs Based on Timing Error Correction.Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin
2005ICCADParametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David T. Blaauw, Dennis Sylvester
2005ICCADAccurate delay computation for noisy waveform shapes.Amit Jain, David T. Blaauw, Vladimir Zolotov
2005ICCADStatic timing analysis considering power supply variations.Sanjay Pant, David T. Blaauw
2005ICCADDiscrete Vt assignment and gate sizing using a self-snapping continuous formulation.Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David T. Blaauw, Vladimir Zolotov
2005ISCAEnergy Optimization of Subthreshold-Voltage Sensor Network Processors.Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David T. Blaauw
2005ISCASTiming error correction techniques for voltage-scalable on-chip memories.Eric Karl, Dennis Sylvester, David T. Blaauw
2005ISLPEDAnalysis and mitigation of variability in subthreshold design.Bo Zhai, Scott Hanson, David T. Blaauw, Dennis Sylvester
2004ASPDACA simplified transmission-line based crosstalk noise model for on-chip RLC wiring.Kanak Agarwal, Dennis Sylvester, David T. Blaauw
2004DACStatistical gate delay model considering multiple input switching.Aseem Agarwal, Florentin Dartu, David T. Blaauw
2004DACVariational delay metrics for interconnect timing analysis.Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
2004DACLeakage-and crosstalk-aware bus encoding for total power reduction.Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David T. Blaauw
2004DACCircuit-aware architectural simulation.Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
2004DACStatic timing analysis using backward signal propagation.Dongwoo Lee, Vladimir Zolotov, David T. Blaauw
2004DACA stochastic approach To power grid analysis.Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2004DACParametric yield estimation considering leakage variability.Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester
2004DACStatistical optimization of leakage power considering process variations using dual-Vth and sizing.Ashish Srivastava, Dennis Sylvester, David T. Blaauw
2004DACPower minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.Ashish Srivastava, Dennis Sylvester, David T. Blaauw
2004DACTheoretical and practical limits of dynamic voltage scaling.Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztin Flautner
2004DATESimultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester
2004DATEConcurrent Sizing, Vdd and Vth Assignment for Low-Power Design.Ashish Srivastava, Dennis Sylvester, David T. Blaauw
2004ISLPEDReducing pipeline energy demands with local DVS and dynamic retiming.Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
2003ASPDACStatistical delay computation considering spatial correlations.Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda
2003DACComputation and Refinement of Statistical Bounds on Circuit Delay.Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
2003DACAn effective capacitance based driver output model for on-chip RLC interconnects.Kanak Agarwal, Dennis Sylvester, David T. Blaauw
2003DACSimple metrics for slew rate of RC circuits based on two circuit moments.Kanak Agarwal, Dennis Sylvester, David T. Blaauw
2003DACPost-route gate sizing for crosstalk noise reduction.Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
2003DACStatic leakage reduction through simultaneous threshold voltage and state assignment.Dongwoo Lee, David T. Blaauw
2003DACAnalysis and minimization techniques for total leakage considering gate oxide leakage.Dongwoo Lee, Wesley Kwong, David T. Blaauw, Dennis Sylvester
2003DACReshaping EDA for power.Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
2003DACNon-iterative switching window computation for delay-noise.Bhavana Thudi, David T. Blaauw
2003DATEStatistical Timing Analysis Using Bounds.Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
2003ICCADStatistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.Aseem Agarwal, David T. Blaauw, Vladimir Zolotov
2003ICCADStatistical Clock Skew Analysis Considering Intra-Die Process Variations.Aseem Agarwal, David T. Blaauw, Vladimir Zolotov
2003ICCADAU: Timing Analysis Under Uncertainty.Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2003ICCADLeakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches.Nam Sung Kim, David T. Blaauw, Trevor N. Mudge
2003ICCADSOI Transistor Model for Fast Transient Simulation.D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel
2003ICCADVectorless Analysis of Supply Noise Induced Delay Variation.Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2003ICCDOptimal Inductance for On-chip RLC Interconnections.Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester
2003ISCASTable look-up based compact modeling for on-chip interconnect timing and noise analysis.Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2003ISLPEDStatistical estimation of leakage current considering inter- and intra-die process variation.Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester
2003MICRORazor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztin Flautner, Trevor N. Mudge
2002DACEstimation of the likelihood of capacitive coupling noise.Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul
2002DATEAnalysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
2002ICCADEstimation of signal arrival times in the presence of delay noise.Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2002ICCADEfficient crosstalk noise modeling using aggressor and tree reductions.Li Ding, David T. Blaauw, Pinaki Mazumder
2002ICCADA precorrected-FFT method for simulating on-chip inductance.Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2002ICCADCombined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.Steven M. Martin, Krisztin Flautner, Trevor N. Mudge, David T. Blaauw
2002ICCADNoise propagation and failure criteria for VLSI designs.Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
2002ISCADrowsy Caches: Simple Techniques for Reducing Leakage Power.Krisztin Flautner, Nam Sung Kim, Steven M. Martin, David T. Blaauw, Trevor N. Mudge
2002ISCASCrosstalk noise estimation using effective coupling capacitance.Li Ding, Pinaki Mazumder, David T. Blaauw
2002ISLPEDModeling and analysis of leakage power considering within-die process variations.Ashish Srivastava, Robert Bai, David T. Blaauw, Dennis Sylvester
2002MICRODrowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.Nam Sung Kim, Krisztin Flautner, David T. Blaauw, Trevor N. Mudge
2001DACInductance 101: Analysis and Design Issues.Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
2001DACDriver Modeling and Alignment for Worst-Case Delay Noise.Supamas Sirichotiyakul, David T. Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
2001ICCADFalse-Noise Analysis using Logic Implications.Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov
2001ISLPEDOn the interaction of power distribution network with substrate.Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
2000DACRemoving user specified false paths from timing graphs.David T. Blaauw, Rajendran Panda, Abhijit Das
2000DACCurrent signature compression for IR-drop analysis.Rajat Chaudhry, David T. Blaauw, Rajendran Panda, Tim Edwards
2000DACOn-chip inductance modeling and analysis.Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw
2000DACClariNet: a noise analysis tool for deep submicron design.Rafi Levy, David T. Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov
2000DACHierarchical analysis of power distribution networks.Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw
2000ICCADSlope Propagation in Static Timing Analysis.David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
2000ISLPEDModel and analysis for combined package and on-chip power grid simulation.Rajendran Panda, David T. Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
2000VLSIDDesign and Analysis of Power Distribution Networks with Accurate RLC Models.Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw
1999DACStand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw
1999VLSIDA Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury
1998DACDesign and Analysis of Power Distribution Networks in PowerPC Microprocessors.Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
1998DACMigration: A New Technique to Improve Synthesized Designs Through Incremental Customization.Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw
1998ISLPEDEmerging power management tools for processor design.David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
1997DATEFast power loss calculation for digital static CMOS circuits.Sergey Gavrilov, Alexey Glebov, Sergey G. Rusakov, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan
1997ICCADLibrary-less synthesis for static CMOS combinational logic circuits.Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
1997ICCDTransistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor.Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning
1995ISLPEDTransistor reordering for low power CMOS gates using an SP-BDD representation.Alexey Glebov, David T. Blaauw, Larry G. Jones
1990ICCADSNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction.David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
1990ICCDAutomatic classification of node types in switch-level descriptions.David T. Blaauw, Prithviraj Banerjee, Jacob A. Abraham
1990ICCDFault grading of large digital systems.Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham
1989DACAutomatic Generation of Behavioral Models from Switch-Level Descriptions.David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh
1988ICCADCHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits.Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh