Grschwin Fey
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
96
Venues
25
Active years
2003–2026
Best venue rank
A*
Where they publish
- CDDECS15 papers
- CDSD14 papers
- ADATE11 papers
- BETS9 papers
- CFDL6 papers
- BASPDAC5 papers
- NationalVLSID4 papers
- AICCAD3 papers
- A*DAC3 papers
- CMEMOCODE3 papers
- CDX2 papers
- CEJC2 papers
- CETFA2 papers
- BGI2 papers
- CIOLTS2 papers
- BFMCAD2 papers
- CISCAS2 papers
- CRSP2 papers
- NationalBTW1 paper
- CIPIN1 paper
- ARE1 paper
- BCOMPSAC1 paper
- CPDP1 paper
- AICST1 paper
- UnrankedEDCC1 paper
Papers
96 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Automated Self-Explanation of Expected versus Perceived Behavior for Interacting Digital Systems. | Mohammad Alkhiyami, Gianluca Martino, Grschwin Fey |
| 2026 | DDECS | Ageing Monitoring for Commercial Microcontrollers Based on Timing Windows. | Leandro Lanzieri, Jir Krl, Grschwin Fey, Holger Schlarb, Thomas C. Schmidt |
| 2026 | ETS | Auto-Generating Ageing Self-Tests with Hardware in the Loop for Commercial Microcontrollers. | Leandro Lanzieri, Grschwin Fey, Holger Schlarb, Thomas C. Schmidt |
| 2025 | DATE | Specification Mining Facing Generative AI. | Grschwin Fey, Harry Foster, Tara Ghasempuri, Badri Gopalan, Jrg Mller, Manish Pandey |
| 2025 | DX | One-Shot Learning in Hybrid System Identification: A New Modular Paradigm. | Swantje Plambeck, Maximilian Schmidt, Louise Trav-Massuys, Grschwin Fey |
| 2025 | ETS | European Test Symposium Teams: an Anniversary Snapshot. | Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilrd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersgl, Grschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard, Marcello Traiola, Arnaud Virazel, Fernando Fernandes dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letcia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, Fabian Luis Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand |
| 2025 | FDL | Leveraging the Benefits of Information Flow Tracking for Detecting Hardware Design Flaws. | Srinidhi Rathnakar Ganiga, Bernhard J. Berger, Grschwin Fey |
| 2025 | VLSID | DuRTL - Information Flow Analysis Tool for Register Transfer Level Hardware Designs. | Lutz Schammer, Gianluca Martino, Grschwin Fey |
| 2024 | DSD | Studying the Degradation of Propagation Delay on FPGAs at the European XFEL. | Leandro Lanzieri, Lukasz Butkowski, Jir Krl, Grschwin Fey, Holger Schlarb, Thomas C. Schmidt |
| 2024 | DX | Usability of Symbolic Regression for Hybrid System Identification - System Classes and Parameters (Short Paper). | Swantje Plambeck, Maximilian Schmidt, Audine Subias, Louise Trav-Massuys, Grschwin Fey |
| 2024 | EJC | Data-Driven Fault Localization in Cyber-Physical Systems Using Dependency Graphs and Anomaly Detection. | Arne Grnhagen, Annika Eichler, Marina Tropmann-Frick, Grschwin Fey |
| 2023 | BTW | Predictive Maintenance for the Optical Synchronization System of the European XFEL: A Systematic Literature Survey. | Arne Grnhagen, Marina Tropmann-Frick, Annika Eichler, Grschwin Fey |
| 2023 | DATE | DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation. | Hany Abdelmaksoud, Zain Alabedin Haj Hammadeh, Grschwin Fey, Daniel Ldtke |
| 2023 | DDECS | Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models. | Swantje Plambeck, Grschwin Fey |
| 2023 | DSD | Latency-Optimized Hardware Acceleration of Multilayer Perceptron Inference. | Ahmad Al-Zoubi, Benedikt Schaible, Gianluca Martino, Grschwin Fey |
| 2023 | DSD | Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning. | Leandro Lanzieri, Peter Kietzmann, Grschwin Fey, Holger Schlarb, Thomas C. Schmidt |
| 2023 | EJC | Data-Based Condition Monitoring and Disturbance Classification in Actively Controlled Laser Oscillators. | Arne Grnhagen, Annika Eichler, Marina Tropmann-Frick, Grschwin Fey |
| 2023 | ETFA | Towards the Automatic Generation of Models for Prediction, Monitoring, and Testing of Cyber-Physical Systems. | Markus Knitt, Swantje Plambeck, Jan Christian Wieck, Julian Kohlisch, Stephan Balduin, Eric M. S. P. Veith, Jakob Schyga, Johannes Hinckeldeyn, Grschwin Fey, Jochen Kreutzfeldt |
| 2023 | ETS | FINaL: Driving High-Level Fault Injection Campaigns with Natural Language. | Khaled Galal Abdelwahab Abdelaziz, Ralph Grgen, Grschwin Fey |
| 2023 | GI | Informatik fr Ingenieure an der Technischen Universitt Hamburg. | Bernhard J. Berger, Grschwin Fey |
| 2022 | ASPDAC | On the Viability of Decision Trees for Learning Models of Systems. | Swantje Plambeck, Lutz Schammer, Grschwin Fey |
| 2022 | ETFA | Decision Tree Models of Continuous Systems. | Swantje Plambeck, Grschwin Fey |
| 2022 | IPIN | Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. | Jakob Schyga, Swantje Plambeck, Johannes Hinckeldeyn, Grschwin Fey, Jochen Kreutzfeldt |
| 2022 | RE | Self-Explanation in Systems of Systems. | Grschwin Fey, Martin Frnzle, Rolf Drechsler |
| 2021 | COMPSAC | Learning Models of Cyber-Physical Systems using Automata Learning. | Lutz Schammer, Swantje Plambeck, Fin Hendrik Bahnsen, Grschwin Fey |
| 2021 | DSD | Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems. | Gianluca Martino, Arne Grnhagen, Julien Branlard, Annika Eichler, Grschwin Fey, Holger Schlarb |
| 2021 | DSD | Metrics for the Evaluation of Approximate Sequential Streaming Circuits. | Swantje Plambeck, Gianluca Martino, Grschwin Fey |
| 2021 | ETS | Designing Recurrent Neural Networks for Monitoring Embedded Devices. | Fin Hendrik Bahnsen, Jan Kaiser, Grschwin Fey |
| 2020 | DSD | Revisiting Explicit Enumeration for Exact Synthesis. | Gianluca Martino, Heinz Riener, Grschwin Fey |
| 2019 | DSD | Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks. | Fin Hendrik Bahnsen, Grschwin Fey |
| 2019 | ETS | Symbolic Circuit Analysis under an Arc Based Timing Model. | Grschwin Fey, Alberto Garca Ortiz |
| 2019 | FDL | Syntax-Guided Enumeration of Temporal Properties. | Gianluca Martino, Grschwin Fey |
| 2018 | DDECS | Software-Level TMR Approach for On-Board Data Processing in Space Applications. | Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Grschwin Fey |
| 2018 | DDECS | Augmenting All Solution SAT Solving for Circuits with Structural Information. | Abraham Temesgen Tibebu, Grschwin Fey |
| 2017 | ASPDAC | Property mining using dynamic dependency graphs. | Jan Malburg, Tino Flenker, Grschwin Fey |
| 2017 | ASPDAC | CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. | Heinz Riener, Rdiger Ehlers, Grschwin Fey |
| 2017 | DDECS | Mapping abstract and concrete hardware models for design understanding. | Tino Flenker, Grschwin Fey |
| 2017 | IOLTS | Temporal redundancy latch-based architecture for soft error mitigation. | Robert Schmidt, Alberto Garca Ortiz, Grschwin Fey |
| 2016 | DDECS | Exploiting error detection latency for parity-based soft error detection. | Gke Aydos, Grschwin Fey |
| 2016 | ETS | A hybrid algorithm to conservatively check the robustness of circuits. | Niels Thole, Lorena Anghel, Grschwin Fey |
| 2016 | FDL | Designing reliable cyber-physical systems overview associated to the special session at FDL'16. | Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Grschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Knighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Rck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao |
| 2016 | FDL | Equivalence checking on ESL utilizing a priori knowledge. | Niels Thole, Heinz Riener, Grschwin Fey |
| 2016 | ICCAD | Multilevel design understanding: from specification to logic (invited paper). | Sandip Ray, Ian G. Harris, Grschwin Fey, Mathias Soeken |
| 2016 | ICCAD | Exact diagnosis using boolean satisfiability. | Heinz Riener, Grschwin Fey |
| 2016 | IOLTS | On the robustness of DCT-based compression algorithms for space applications. | Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Grschwin Fey, Jan-Gerd Mess, Robert Schmidt |
| 2015 | DDECS | Equivalence Checking on System Level Using a Priori Knowledge. | Niels Thole, Heinz Riener, Grschwin Fey |
| 2015 | GI | Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture. | Gke Aydos, Grschwin Fey |
| 2014 | DDECS | Automatically connecting hardware blocks via light-weight matching techniques. | Jan Malburg, Niklas Krafczyk, Grschwin Fey |
| 2014 | ETS | Sat-based speedpath debugging using waveforms. | Mehdi Dehbashi, Grschwin Fey |
| 2014 | FDL | MetaSMT: a unified interface to SMT-LIB2. | Heinz Riener, Mathias Soeken, Clemens Werther, Grschwin Fey, Rolf Drechsler |
| 2014 | PDP | Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. | Mehdi Dehbashi, Grschwin Fey |
| 2014 | VLSID | Debug Automation for Synchronization Bugs at RTL. | Mehdi Dehbashi, Grschwin Fey |
| 2013 | DATE | Reliability analysis reloaded: how will we survive? | Robert C. Aitken, Grschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda |
| 2013 | DATE | Tuning dynamic data flow analysis to support design understanding. | Jan Malburg, Alexander Finder, Grschwin Fey |
| 2013 | DATE | Improving fault tolerance utilizing hardware-software-co-synthesis. | Heinz Riener, Stefan Frehse, Grschwin Fey |
| 2013 | DDECS | Efficient automated speedpath debugging. | Mehdi Dehbashi, Grschwin Fey |
| 2013 | DDECS | Debugging HDL designs based on functional equivalences with high-level specifications. | Alexander Finder, Jan-Philipp Witte, Grschwin Fey |
| 2012 | DAC | Automated feature localization for hardware designs using coverage metrics. | Jan Malburg, Alexander Finder, Grschwin Fey |
| 2012 | DDECS | Automated debugging from pre-silicon to post-silicon. | Mehdi Dehbashi, Grschwin Fey |
| 2012 | DSD | On Modeling and Evaluation of Logic Circuits under Timing Variations. | Mehdi Dehbashi, Grschwin Fey, Kaushik Roy, Anand Raghunathan |
| 2012 | ETS | Functional analysis of circuits under timing variations. | Mehdi Dehbashi, Grschwin Fey, Kaushik Roy, Anand Raghunathan |
| 2012 | FMCAD | Complete and effective robustness checking by means of interpolation. | Stefan Frehse, Grschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler |
| 2012 | MEMOCODE | Model-based diagnosis versus error explanation. | Heinz Riener, Grschwin Fey |
| 2011 | DAC | Orchestrated multi-level information flow analysis to understand SoCs. | Grschwin Fey |
| 2011 | DDECS | Automatic property generation for the formal verification of bus bridges. | Mathias Soeken, Ulrich Khne, Martin Freibothe, Grschwin Fey, Rolf Drechsler |
| 2011 | DSD | Automated Design Debugging in a Testbench-Based Verification Environment. | Mehdi Dehbashi, Andr Slflow, Grschwin Fey |
| 2011 | ETS | Latency Analysis for Sequential Circuits. | Alexander Finder, Andr Slflow, Grschwin Fey |
| 2011 | FMCAD | metaSMT: Focus on Your Application not on Solver Integration. | Finn Haedicke, Stefan Frehse, Grschwin Fey, Daniel Groe, Rolf Drechsler |
| 2011 | ICST | Test Case Generation from Mutants Using Model Checking Techniques. | Heinz Riener, Roderick Bloem, Grschwin Fey |
| 2010 | DDECS | Formal verification meets robustness checking - Techniques and challenges. | Rolf Drechsler, Grschwin Fey |
| 2010 | DDECS | A better-than-worst-case robustness measure. | Stefan Frehse, Grschwin Fey, Rolf Drechsler |
| 2010 | DSD | RobuCheck: A Robustness Checker for Digital Circuits. | Stefan Frehse, Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2010 | EDCC | RobuCheck: a robustness checker for digital circuits. | Stefan Frehse, Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2010 | FDL | Evaluating Debugging Algorithms from a Qualitative Perspective. | Alexander Finder, Grschwin Fey |
| 2010 | ICCAD | Polynomial datapath optimization using constraint solving and formal modelling. | Finn Haedicke, Bijan Alizadeh, Grschwin Fey, Masahiro Fujita, Rolf Drechsler |
| 2010 | ISCAS | Using QBF to increase accuracy of SAT-based debugging. | Andr Slflow, Grschwin Fey, Rolf Drechsler |
| 2009 | DAC | Computing bounds for fault tolerance using formal techniques. | Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2009 | DATE | Increasing the accuracy of SAT-based debugging. | Andr Slflow, Grschwin Fey, Ccile Braunstein, Ulrich Khne, Rolf Drechsler |
| 2009 | DSD | Robustness Check for Multiple Faults Using Formal Techniques. | Stefan Frehse, Grschwin Fey, Andr Slflow, Rolf Drechsler |
| 2009 | RSP | WoLFram- A Word Level Framework for Formal Verification. | Andr Slflow, Ulrich Khne, Grschwin Fey, Daniel Groe, Rolf Drechsler |
| 2008 | DATE | Automatic Generation of Complex Properties for Hardware Designs. | Frank Rogin, Thomas Klotz, Grschwin Fey, Rolf Drechsler, Steffen Rlke |
| 2008 | DSD | Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. | Robert Wille, Grschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
| 2007 | DDECS | Instance Generation for SAT-based ATPG. | Daniel Tille, Grschwin Fey, Rolf Drechsler |
| 2007 | DSD | On the Construction of Small Fully Testable Circuits with Low Depth. | Grschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler |
| 2007 | ISCAS | SAT-based ATPG for Path Delay Faults in Sequential Circuits. | Stephan Eggersgl, Grschwin Fey, Rolf Drechsler |
| 2007 | MEMOCODE | Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. | Stephan Eggersgl, Grschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jrgen Schlffel |
| 2007 | VLSID | Reusing Learned Information in SAT-based ATPG. | Grschwin Fey, Tim Warode, Rolf Drechsler |
| 2006 | DATE | Avoiding false negatives in formal verification for protocol-driven blocks. | Grschwin Fey, Daniel Groe, Rolf Drechsler |
| 2006 | DATE | On the relation between simulation-based and SAT-based diagnosis. | Grschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
| 2006 | VLSID | An Integrated Approach for Combining BDD and SAT Provers. | Rolf Drechsler, Grschwin Fey, Sebastian Kinder |
| 2005 | ASPDAC | Bridging fault testability of BDD circuits. | Junhao Shi, Grschwin Fey, Rolf Drechsler |
| 2005 | RSP | SyCE: An Integrated Environment for System Design in SystemC. | Rolf Drechsler, Grschwin Fey, Christian Genz, Daniel Groe |
| 2004 | ASPDAC | Improving simulation-based verification by means of formal methods. | Grschwin Fey, Rolf Drechsler |
| 2004 | DATE | Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. | Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Grschwin Fey |
| 2004 | DSD | BDD Circuit Optimization for Path Delay Fault Testability. | Grschwin Fey, Junhao Shi, Rolf Drechsler |
| 2003 | MEMOCODE | Finding Good Counter-Examples to Aid Design Verification. | Grschwin Fey, Rolf Drechsler |