| 2026 | ACL | FastKV: Decoupling of Context Reduction and KV Cache Compression for Prefill-Decoding Acceleration. | Dongwon Jo, Jiwon Song, Yulhwa Kim, Jae-Joon Kim |
| 2026 | DATE | 3D Integration of Hybrid IGZO/Si and IGZO eDRAMs for High-Density/High-Performance On-Chip Memory. | Munhyeon Kim, Sukhyun Choi, Yulhwa Kim, Jae-Joon Kim |
| 2026 | ISLPED | MECA-CiM: A Shared-MicroExponent-aware Configurable Analog Compute-in-Memory Macro for Efficient Inference. | Wonkyung Han, Dohyun Kim, Jihoon Park, Juheun Lee, Sukhyun Choi, Wonjun Han, Jae-Joon Kim |
| 2025 | ACL | L4Q: Parameter Efficient Quantization-Aware Fine-Tuning on Large Language Models. | Hyesung Jeon, Yulhwa Kim, Jae-Joon Kim |
| 2025 | DAC | Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid Bonding. | Sanghyeok Han, Byungkuk Yoon, Gyeonghwan Park, Choungki Song, Dongkyun Kim, Jae-Joon Kim |
| 2025 | DAC | SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIM. | Byungkuk Yoon, Sanghyeok Han, Gyeonghwan Park, Jae-Joon Kim |
| 2025 | DATE | Compute-in-Memory Array Design Using Stacked Hybrid IGZO/Si eDRAM cells. | Munhyeon Kim, Yulhwa Kim, Jae-Joon Kim |
| 2025 | DATE | Integer Unit-Based Outlier-Aware LLM Accelerator Preserving Numerical Accuracy of FP-FP GEMM. | Jehun Lee, Jae-Joon Kim |
| 2025 | DATE | An eDRAM Digital In-Memory Neural Network Accelerator for High-Throughput and Extended Data Retention Time. | Inhwan Lee, Jehun Lee, Jaeyong Jang, Jae-Joon Kim |
| 2025 | DATE | COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Accelerators. | Jihoon Park, Jeongin Choe, Dohyun Kim, Jae-Joon Kim |
| 2025 | DATE | DOTS: DRAM-PIM Optimization for Tall and Skinny GEMM Operations in LLM Inference. | Gyeonghwan Park, Sanghyeok Han, Byungkuk Yoon, Jae-Joon Kim |
| 2025 | ICCAD | LLM-on-the-Palm: Mobile LLM Inference with PIM-Enhanced NAND Flash Memory. | Hyunjin Kim, Sanghyeok Han, Jae-Joon Kim |
| 2025 | ICCAD | Energy-Efficient Accelerator for Scalable Point Transformer Networks with Reduced Data Access. | Hyunsung Yoon, Jehun Lee, Jae-Joon Kim |
| 2025 | ISLPED | Partial-Sum Quantization Based on Pseudo-Quantization Noise for Variation-Tolerant Analog In-Memory Computing. | Nameun Kang, Eunhyeok Park, Sangsu Park, Jongil Kim, Jaeyun Yi, Jae-Joon Kim |
| 2025 | MICRO | CrossBit: Bitwise Computing in NAND Flash Memory with Inter-Bitline Data Communication. | Hyunjin Kim, Seunghwan Song, Sukhyun Choi, Jeongin Choe, Sanghyeok Han, Jisung Park, Jinho Lee, Jae-Joon Kim |
| 2024 | DAC | 4-Transistor Ternary Content Addressable Memory Cell Design using Stacked Hybrid IGZO/Si Transistors. | Munhyeon Kim, Jae-Joon Kim |
| 2024 | DAC | Fused Sampling and Grouping with Search Space Reduction for Efficient Point Cloud Acceleration. | Hyunsung Yoon, Jae-Joon Kim |
| 2024 | HPCA | FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy. | Jaeyong Jang, Yulhwa Kim, Juheun Lee, Jae-Joon Kim |
| 2024 | ICML | SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. | Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim |
| 2023 | DAC | In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time. | Inhwan Lee, Eunhwan Kim, Nameun Kang, Hyunmyung Oh, Jae-Joon Kim |
| 2023 | ICCAD | Efficient Sampling and Grouping Acceleration for Point Cloud Deep Learning via Single Coordinate Comparison. | Hyunsung Yoon, Jae-Joon Kim |
| 2023 | ICCV | INSTA-BNN: Binary Neural Network with INSTAnce-aware Threshold. | Changhun Lee, Hyungjun Kim, Eunhyeok Park, Jae-Joon Kim |
| 2023 | ICLR | Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic. | Yulhwa Kim, Jaeyong Jang, Jehun Lee, Jihoon Park, Jeonghoon Kim, Byeongwook Kim, Baeseong Park, Se Jung Kwon, Dongsoo Lee, Jae-Joon Kim |
| 2023 | WACV | Searching for Robust Binary Neural Networks via Bimodal Parameter Perturbation. | Daehyun Ahn, Hyungjun Kim, Taesu Kim, Eunhyeok Park, Jae-Joon Kim |
| 2022 | DAC | TAIM: ternary activation in-memory computing hardware with 6T SRAM array. | Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim |
| 2022 | ICCAD | Workload-Balanced Graph Attention Network Accelerator with Top-K Aggregation Candidates. | Naebeom Park, Daehyun Ahn, Jae-Joon Kim |
| 2021 | CVPR | Improving Accuracy of Binary Neural Networks Using Unbalanced Activation Distribution. | Hyungjun Kim, Jihoon Park, Changhun Lee, Jae-Joon Kim |
| 2021 | DATE | Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. | Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim |
| 2021 | DATE | SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching. | Sungju Ryu, Youngtaek Oh, Taesu Kim, Daehyun Ahn, Jae-Joon Kim |
| 2021 | ICCAD | Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow. | Sungju Ryu, Youngtaek Oh, Jae-Joon Kim |
| 2020 | DAC | Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. | Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim |
| 2020 | FPGA | V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning. | Taesu Kim, Daehyun Ahn, Jae-Joon Kim |
| 2020 | ICCAD | Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. | Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim |
| 2020 | ICLR | BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations. | Hyungjun Kim, Kyungsu Kim, Jinseok Kim, Jae-Joon Kim |
| 2020 | ISLPED | Time-step interleaved weight reuse for LSTM neural network computing. | Naebeom Park, Yulhwa Kim, Daehyun Ahn, Taesu Kim, Jae-Joon Kim |
| 2019 | ASPDAC | In-memory batch-normalization for resistive memory based binary neural network hardware. | Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim |
| 2019 | DAC | Peregrine: A Flexible Hardware Accelerator for LSTM with Limited Synaptic Connection Patterns. | Jaeha Kung, Junki Park, Sehun Park, Jae-Joon Kim |
| 2019 | DAC | BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation. | Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jae-Joon Kim |
| 2019 | DATE | Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array. | Wooseok Yi, Yulhwa Kim, Jae-Joon Kim |
| 2019 | ICLR | Double Viterbi: Weight Encoding for High Compression Ratio and Fast On-Chip Reconstruction for Deep Neural Network. | Daehyun Ahn, Dongsoo Lee, Taesu Kim, Jae-Joon Kim |
| 2018 | DATE | Maximizing system performance by balancing computation loads in LSTM accelerators. | Junki Park, Jaeha Kung, Wooseok Yi, Jae-Joon Kim |
| 2018 | ICLR | Viterbi-based Pruning for Sparse Matrix with Fixed and High Index Compression Ratio. | Dongsoo Lee, Daehyun Ahn, Taesu Kim, Pierce I-Jen Chuang, Jae-Joon Kim |
| 2018 | ISLPED | Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array. | Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, Jae-Joon Kim |
| 2018 | ISLPED | Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. | Jinseok Kim, Yulhwa Kim, Sungho Kim, Jae-Joon Kim |
| 2017 | ISLPED | Low design overhead timing error correction scheme for elastic clock methodology. | Sungju Ryu, Jongeun Koo, Jae-Joon Kim |
| 2017 | RSP | GeCo: classification restricted Boltzmann machine hardware for on-chip learning. | Wooseok Yi, Junki Park, Jae-Joon Kim |
| 2014 | ASPDAC | Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. | Insup Shin, Jae-Joon Kim, Youngsoo Shin |
| 2014 | DATE | Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs. | Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee |
| 2013 | ISLPED | A pipeline architecture with 1-cycle timing error correction for low voltage operations. | Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin |
| 2011 | ISLPED | Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. | Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy |
| 2008 | ISCAS | Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
| 2008 | VLSID | Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. | Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy |
| 2008 | VLSID | On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. | Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown |
| 2008 | VTS | Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy |
| 2006 | ISLPED | Robust level converter design for sub-threshold logic. | Ik Joon Chang, Jae-Joon Kim, Kaushik Roy |
| 2003 | ISLPED | A forward body-biased low-leakage SRAM cache: device and architecture considerations. | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy |