| 2026 | ASPDAC | ARCS: Architecture-Responsive CGRA Scheduling. | Omar Ragheb, Jason Helge Anderson |
| 2026 | DATE | CUT-MC: Optimizing the Relationship Between Context Count, Unrolling and Throughput in Multi-Context CGRAs. | Stephen Wicklund, Jason Helge Anderson |
| 2025 | FPGA | FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. | Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne |
| 2024 | DAC | CLUMAP: Clustered Mapper for CGRAs with Predication. | Omar Ragheb, Jason Helge Anderson |
| 2024 | FCCM | Mapping Enumeration for Multi-Context CGRAs Using Zero-Suppressed Binary Decision Diagrams. | Rami Beidas, Jason Helge Anderson |
| 2023 | ASPDAC | Area-Driven FPGA Logic Synthesis Using Reinforcement Learning. | Guanglei Zhou, Jason Helge Anderson |
| 2023 | FPL | GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. | Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson |
| 2022 | ASPDAC | CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. | Rami Beidas, Jason Helge Anderson |
| 2022 | ASPDAC | Streaming Accuracy: Characterizing Early Termination in Stochastic Computing. | Hsuan Hsiao, Joshua San Miguel, Jason Helge Anderson |
| 2022 | FPL | Modeling and Exploration of Elastic CGRAs. | Omar Ragheb, Tianyi Yu, David Ma, Jason Helge Anderson |
| 2021 | ASPDAC | Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. | Hsuan Hsiao, Joshua San Miguel, Yuko Hara-Azumi, Jason Helge Anderson |
| 2021 | ASPDAC | High-Level Synthesis of Transactional Memory. | Omar Ragheb, Jason Helge Anderson |
| 2021 | DSD | An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems. | Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson |
| 2021 | FPL | Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. | Jin Hee Kim, Jason Helge Anderson |
| 2019 | ASPDAC | XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration. | Hyeon Uk Sim, Jason Helge Anderson, Jongeun Lee |
| 2019 | DAC | Thread Weaving: Static Resource Scheduling for Multithreaded High-Level Synthesis. | Hsuan Hsiao, Jason Helge Anderson |
| 2019 | FCCM | Impact of FPGA Architecture on Area and Performance of CGRA Overlays. | Ian Taras, Jason Helge Anderson |
| 2019 | FCCM | Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. | Matthew J. P. Walker, Jason Helge Anderson |
| 2019 | FPGA | EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. | Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides |
| 2019 | FPL | A Dynamic Memory Allocation Library for High-Level Synthesis. | Nicholas V. Giamblanco, Jason Helge Anderson |
| 2018 | DAC | An architecture-agnostic integer linear programming approach to CGRA mapping. | S. Alexander Chin, Jason Helge Anderson |
| 2018 | DATE | High-level synthesis of software-customizable floating-point cores. | Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson |
| 2018 | DATE | Sensei: An area-reduction advisor for FPGA high-level synthesis. | Hsuan Hsiao, Jason Helge Anderson |
| 2018 | FCCM | High-Level Synthesis of FPGA Circuits with Multiple Clock Domains. | Omar Ragheb, Jason Helge Anderson |
| 2017 | FPL | Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. | Yu Ting Chen, Jason Helge Anderson |
| 2016 | DATE | Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. | Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita |
| 2016 | FPGA | Towards PVT-Tolerant Glitch-Free Operation in FPGAs. | Safeen Huda, Jason Helge Anderson |
| 2016 | FPL | Preface. | Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele |
| 2015 | DATE | Profiling-driven multi-cycling in FPGA high-level synthesis. | Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Helge Anderson |
| 2015 | EUC | Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC. | Tanvir Ahmed, Noriaki Sakamoto, Jason Helge Anderson, Yuko Hara-Azumi |
| 2015 | FPL | Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. | Jin Hee Kim, Jason Helge Anderson |
| 2015 | FPL | Significant papers from the first 25 years of the FPL conference. | Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, Joo M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang |
| 2014 | ASPLOS | Power Modeling for Heterogeneous Processors. | Tahir Diop, Natalie D. Enright Jerger, Jason Helge Anderson |
| 2014 | EUC | Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. | Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson |
| 2014 | FCCM | On Hard Adders and Carry Chains in FPGAs. | Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz |
| 2014 | FPGA | Optimizing effective interconnect capacitance for FPGA power reduction. | Safeen Huda, Jason Helge Anderson, Hirotaka Tamura |
| 2014 | FPGA | Towards interconnect-adaptive packing for FPGAs. | Jason Luu, Jonathan Rose, Jason Helge Anderson |
| 2014 | FPL | Source-level debugging for FPGA high-level synthesis. | Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson |
| 2014 | FPL | Modulo SDC scheduling with recurrence minimization in high-level synthesis. | Andrew Canis, Stephen Dean Brown, Jason Helge Anderson |
| 2013 | ASPDAC | Range and bitmask analysis for hardware optimization in high-level synthesis. | Marcel Gort, Jason Helge Anderson |
| 2013 | CASES | From software to accelerators with LegUp high-level synthesis. | Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson |
| 2013 | DATE | Multi-pumping for resource reduction in FPGA high-level synthesis. | Andrew Canis, Jason Helge Anderson, Stephen Dean Brown |
| 2013 | FCCM | The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. | Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Brown, Jason Helge Anderson |
| 2013 | FPGA | High-level synthesis with LegUp: a crash course for users and researchers. | Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi |
| 2013 | FPL | Charge recycling for power reduction in FPGA interconnect. | Safeen Huda, Jason Helge Anderson, Hirotaka Tamura |
| 2013 | MASCOTS | DistCL: A Framework for the Distributed Execution of OpenCL Kernels. | Tahir Diop, Steven Gurfinkel, Jason Helge Anderson, Natalie D. Enright Jerger |
| 2012 | DATE | Leveraging reconfigurability to raise productivity in FPGA functional debug. | Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le |
| 2012 | FCCM | Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. | Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski |
| 2012 | FPGA | Impact of FPGA architecture on resource sharing in high-level synthesis. | Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Brown, Tomasz S. Czajkowski |
| 2012 | FPGA | The VTR project: architecture and CAD for FPGAs from verilog to routing. | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson |
| 2012 | FPGA | Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. | Warren Wai-Kit Shum, Jason Helge Anderson |
| 2012 | FPL | Analytical placement for heterogeneous FPGAs. | Marcel Gort, Jason Helge Anderson |
| 2011 | ASPDAC | Area-efficient FPGA logic elements: Architecture and synthesis. | Jason Helge Anderson, Qiang Wang |
| 2011 | ASPDAC | An integer programming placement approach to FPGA clock power reduction. | Alireza Rakhshanfar, Jason Helge Anderson |
| 2011 | FPGA | LegUp: high-level synthesis for FPGA-based processor/accelerator systems. | Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski |
| 2011 | FPGA | Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. | Jason Luu, Jason Helge Anderson, Jonathan Rose |
| 2011 | FPL | Reducing FPGA Router Run-Time through Algorithm and Architecture. | Marcel Gort, Jason Helge Anderson |
| 2011 | FPL | Latch-Based Performance Optimization for FPGAs. | Bill Teng, Jason Helge Anderson |
| 2011 | ISLPED | FPGA glitch power analysis and reduction. | Warren Wai-Kit Shum, Jason Helge Anderson |
| 2010 | ASPDAC | A PUF design for secure FPGA-based embedded systems. | Jason Helge Anderson |
| 2010 | FPGA | FPGA power reduction by guarded evaluation. | Jason Helge Anderson, Chirag Ravishankar |
| 2009 | FPGA | Emerging application domains: research challenges and opportunities for FPGAs. | Jason Helge Anderson |
| 2009 | FPGA | Clock power reduction for virtex-5 FPGAs. | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
| 2009 | FPL | Improving logic density through synthesis-inspired architecture. | Jason Helge Anderson, Qiang Wang |
| 2009 | FPL | Clock gating architectures for FPGA power reduction. | Safeen Huda, Muntasir Mallick, Jason Helge Anderson |
| 2008 | FPGA | Architecture-specific packing for virtex-5 FPGAs. | Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal |
| 2004 | ASPDAC | Interconnect capacitance estimation for FPGAs. | Jason Helge Anderson, Farid N. Najm |
| 2004 | FPGA | Active leakage power optimization for FPGAs. | Jason Helge Anderson, Farid N. Najm, Tim Tuan |
| 2004 | FPL | Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. | Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng |
| 2004 | ICCAD | Low-power programmable routing circuitry for FPGAs. | Jason Helge Anderson, Farid N. Najm |
| 2000 | FPL | A Placement Algorithm for FPGA Designs with Multiple I/O Standards. | Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman |
| 1998 | DAC | Technology Mapping for Large Complex PLDs. | Jason Helge Anderson, Stephen Dean Brown |
| 1998 | FPGA | An LPGA with Foldable PLA-style Logic Blocks. | Jason Helge Anderson, Stephen Dean Brown |