Joan Figueras
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
62
Venues
8
Active years
1991–2017
Best venue rank
B
Where they publish
Papers
62 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ETS | Mitigating read & write errors in STT-MRAM memories under DVS. | Elena-Ioana Vatajelu, Rosa Rodrguez-Montas, Michel Renovell, Joan Figueras |
| 2015 | DATE | Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. | Elena I. Vatajelu, Rosa Rodrguez-Montas, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras |
| 2015 | ETS | Power-aware voltage tuning for STT-MRAM reliability. | Elena I. Vatajelu, Rosa Rodrguez-Montas, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras |
| 2014 | ETS | M-S specification binning based on digitally coded indirect measurements. | lvaro Gmez-Pau, Luz Balado, Joan Figueras |
| 2014 | ETS | Post-bond test of Through-Silicon Vias with open defects. | Rosa Rodrguez-Montas, Daniel Arum, Joan Figueras |
| 2014 | IOLTS | Pre-bond testing of weak defects in TSVs. | Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras |
| 2013 | ETS | BIST architecture to detect defects in tsvs during pre-bond testing. | Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras |
| 2013 | ETS | M-S test based on specification validation using octrees in the measure space. | lvaro Gmez-Pau, Luz Balado, Joan Figueras |
| 2012 | DATE | Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation. | Elena I. Vatajelu, Joan Figueras |
| 2011 | DATE | Robustness analysis of 6T SRAMs in memory retention mode under PVT variations. | Elena I. Vatajelu, Joan Figueras |
| 2011 | DDECS | Statistical analysis of 6T SRAM data retention voltage under process variation. | Elena-Ioana Vatajelu, Joan Figueras |
| 2011 | IOLTS | New reliability mechanisms in memory design for sub-22nm technologies. | Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio Gonzlez, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanaus Ramrez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber |
| 2011 | IOLTS | Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies. | Madalin Neagu, Liviu Miclea, Joan Figueras |
| 2010 | DATE | Analog circuit test based on a digital signature. | Alvaro Gmez, Ricard Sanahuja, Luz Balado, Joan Figueras |
| 2010 | ETS | Diagnosis of full open defects in interconnect lines with fan-out. | Rosa Rodrguez-Montas, Daniel Arum, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman |
| 2010 | ETS | Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. | Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras |
| 2008 | ITC | Time-dependent Behaviour of Full Open Defects in Interconnect Lines. | Rosa Rodrguez-Montas, Daniel Arum, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman |
| 2008 | VTS | Full Open Defects in Nanometric CMOS. | Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman |
| 2007 | VTS | Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. | Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi |
| 2007 | VTS | Diagnosis of Full Open Defects in Interconnecting Lines. | Rosa Rodrguez-Montas, Daniel Arum, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi |
| 2006 | DDECS | Lissajous Based Mixed-Signal Testing for N-Observable Signals. | Luz Balado, Emili Lupon, L. Garca, Rosa Rodrguez-Montas, Joan Figueras |
| 2005 | ETS | Defective behaviours of resistive opens in interconnect lines. | Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras |
| 2004 | ETS | Signal integrity verification using high speed monitors. | Victor Avendao, Vctor H. Champac, Joan Figueras |
| 2004 | VTS | BIST Technique by Equally Spaced Test Vector Sequences. | Salvador Manich, L. Garca, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodrguez-Montas, Joan Figueras |
| 2003 | ETS | Signal integrity loss in bus lines due to open shielding defects. | Victor Avendao, Vctor H. Champac, Joan Figueras |
| 2003 | ETS | On the selection of efficient arithmetic additive test pattern generators [logic test]. | Salvador Manich, L. Garca, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodrguez-Montas, Joan Figueras |
| 2002 | IOLTS | Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. | Rosa Rodrguez-Montas, D. Muoz, Luz Balado, Joan Figueras |
| 2002 | ITC | RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. | Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira, Salvador Manich, Rosa Rodrguez-Montas, Joan Figueras |
| 2001 | ITC | IS-FPGA : a new symmetric FPGA architecture with implicit scan. | Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 2000 | ETS | LEAP: An accurate defect-free I | Antoni Ferr, Joan Figueras |
| 2000 | ETS | Analyzing the test generation problem for an application-oriented test of FPGAs. | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
| 2000 | ITC | Digital signature proposal for mixed-signal circuits. | Anna Maria Brosa, Joan Figueras |
| 1999 | DATE | Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1999 | DATE | Exploring the Combination of IDDQ and iDDt Testing: Energy Testing. | Josep Rius, Joan Figueras |
| 1999 | ETS | On maximizing the coverage of catastrophic and parametric faults. | Anna Maria Brosa, Joan Figueras |
| 1999 | ETS | Low power BIST by filtering non-detecting vectors. | Salvador Manich, A. Gabarr, M. Lopez, Joan Figueras, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Joo Paulo Teixeira, Marcelino B. Santos |
| 1999 | ETS | Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1999 | ISCAS | Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. | Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Joo Paulo Teixeira, Marcelino B. Santos |
| 1998 | DATE | Novel Technique for Testing FPGAs. | Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi |
| 1998 | DATE | RAM-Based FPGA's: A Test Approach for the Configurable Logic. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | DATE | Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. | Rosa Rodrguez-Montas, Joan Figueras |
| 1998 | FPL | SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | ITC | SRAM-based FPGA's: testing the LUT/RAM modules. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | VTS | IDDQ Testing of Opens in CMOS SRAMs. | Vctor H. Champac, Jos Castillejos, Joan Figueras |
| 1997 | DATE | Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. | Salvador Manich, Joan Figueras |
| 1997 | ITC | I | Antoni Ferr, Joan Figueras |
| 1997 | VTS | Power Dissipation During Testing: Should We Worry About it? | Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian |
| 1997 | VTS | Test of RAM-based FPGA: methodology and application to the interconnect. | Michel Renovell, Joan Figueras, Yervant Zorian |
| 1997 | VTS | Bridges in sequential CMOS circuits: current-voltage signatur. | Rosa Rodrguez-Montas, Joan Figueras |
| 1996 | DATE | Power Optimization of Delay Constrained CMOS Bus Drivers. | S. Caufape, Joan Figueras |
| 1996 | DATE | Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations. | Michael Nicolaidis, Salvador Manich, Joan Figueras |
| 1996 | VTS | On estimating bounds of the quiescent current for I | Antoni Ferr, Joan Figueras |
| 1996 | VTS | Enhancing realistic fault secureness in parity prediction array arithmetic operators by I | Salvador Manich, Michael Nicolaidis, Joan Figueras |
| 1995 | DATE | A built-in quiescent current monitor for CMOS VLSI circuits. | Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo, P. De Pauw, Jaume Segura |
| 1995 | DATE | Synthesis of I | Hans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Caldern |
| 1995 | VTS | Testability of floating gate defects in sequential circuits. | Vctor H. Champac, Joan Figueras |
| 1995 | VTS | Detecting I | Josep Rius, Joan Figueras |
| 1994 | VTS | Analysis of I | Eugeni Isern, Joan Figueras |
| 1993 | ITC | Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits. | Eugeni Isern, Joan Figueras |
| 1993 | VTS | Analysis of redundant structures in combinational circuits. | Eugeni Isern, Joan Figueras |
| 1992 | ITC | Bridging Defects Resistance Measurements in a CMOS Process. | Rosa Rodrguez-Montas, Joan Figueras, Eric Bruls |
| 1991 | ITC | Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. | Rosa Rodrguez-Montas, Jaume A. Segura, Vctor H. Champac, Joan Figueras, J. A. Rubio |