| 2019 | ICCAD | Strengthening PUFs using Composition. | Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev, Mahesh V. Tripunitara |
| 2018 | ETS | Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. | Dhruv Patel, Derek Wright, Manoj Sachdev |
| 2015 | FPGA | An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). | Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev |
| 2015 | ICCD | VLSI implementation of high-throughput, low-energy, configurable MIMO detector. | Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet |
| 2011 | ISLPED | Design and analysis of metastable-hardened flip-flops in sub-threshold region. | David Li, Pierce Chuang, David Nairn, Manoj Sachdev |
| 2009 | ISCAS | Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic. | Pierce Chuang, David Li, Manoj Sachdev |
| 2008 | ISCAS | A fully digital ADC using a new delay element with enhanced linearity. | Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev |
| 2007 | ISCAS | A Novel Tri-State Binary Phase Detector. | David Rennie, Manoj Sachdev |
| 2006 | ISCAS | A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization. | Mohammad Sharifkhani, Manoj Sachdev |
| 2006 | ISLPED | A low power SRAM architecture based on segmented virtual grounding. | Mohammad Sharifkhani, Manoj Sachdev |
| 2005 | ISCAS | A 0.8V Delta-Sigma modulator using DTMOS technique. | Mohammad Maymandi-Nejad, Manoj Sachdev |
| 2005 | ITC | Word line pulsing technique for stability fault detection in SRAM cells. | Andrei Pavlov, Mohamed Azimane, Jos Pineda de Gyvez, Manoj Sachdev |
| 2004 | DAC | Design optimizations for microprocessors at low temperature. | Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De |
| 2004 | ISCAS | Modeling and designing energy-delay optimized wide domino circuits. | Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev |
| 2004 | ISCAS | Low power dual matchline ternary content addressable memory. | Nitin Mohan, Manoj Sachdev |
| 2004 | ISLPED | A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. | Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy |
| 2004 | ISLPED | Efficient adaptive voltage scaling system through on-chip critical path emulation. | Mohamed Elgebaly, Manoj Sachdev |
| 2004 | ITC | A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. | Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi |
| 2004 | ITC | AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. | Andrei Pavlov, Manoj Sachdev, Jos Pineda de Gyvez |
| 2003 | DATE | DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. | Muhammad Nummer, Manoj Sachdev |
| 2003 | ISLPED | Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. | Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar |
| 2003 | ITC | Burn-in Temperature Projections for Deep Sub-micron Technologies. | Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins |
| 2003 | ITC | Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. | Derek Wright, Manoj Sachdev |
| 2002 | ITC | A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. | Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi |
| 2002 | ITC | Multi-Gigahertz Digital Test Challenges and Techniques. | Manoj Sachdev |
| 2002 | VLSID | Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). | Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta |
| 2001 | ISLPED | Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. | James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De |
| 2001 | VTS | A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. | Muhammad Nummer, Manoj Sachdev |
| 2000 | ETS | Bridging the testing speed gap: design for delay testability. | Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani |
| 2000 | ITC | Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. | Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De |
| 2000 | VTS | A Low-Speed BIST Framework for High-Performance Circuit Testing. | Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev |
| 1999 | ITC | A DFT technique for high performance circuit testing. | Mansour Shashaani, Manoj Sachdev |
| 1998 | ITC | Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. | Manoj Sachdev, Peter Janssen, Victor Zieren |
| 1997 | DATE | Deep sub-micron I | Manoj Sachdev |
| 1996 | DATE | Test and Testability Techniques for Open Defects in RAM Address Decoders. | Manoj Sachdev |
| 1996 | ISLPED | Low power, testable dual edge triggered flip-flops. | Rafael Llopis, Manoj Sachdev |
| 1996 | ITC | Deep Sub-micron I | Manoj Sachdev |
| 1995 | DATE | Defect-oriented test methodology for complex mixed-signal circuits. | F. C. M. Kuijstermans, Manoj Sachdev, A. P. Thijssen |
| 1995 | ITC | I | Manoj Sachdev |
| 1995 | ITC | Industrial Relevance of Analog IFA: A Fact or a Fiction. | Manoj Sachdev, Bert Atzema |
| 1993 | ITC | Development of Fault Model and Test Algorithms for Embedded DRAMs. | Manoj Sachdev, Math Verstraelen |