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Paolo Prinetto

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

117

Venues

23

Active years

1979–2025

Best venue rank

A*

Where they publish

Papers

117 indexed papers, newest first.

YearVenueTitleAuthors
2025ETSEuropean Test Symposium Teams: an Anniversary Snapshot.Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilrd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersgl, Grschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard, Marcello Traiola, Arnaud Virazel, Fernando Fernandes dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letcia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, Fabian Luis Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2023DASCTowards Cybersecurity Risk Assessment Automation: an Ontological Approach.Nicol Maunero, Fabio De Rosa, Paolo Prinetto
2022ETSReal-Time Control-Flow Integrity for Multicore Mixed-Criticality IoT Systems.Vahid Eftekhari Moghadam, Paolo Prinetto, Gianluca Roascio
2017EDUCONStandards-based tools and services for building lifelong learning pathways.Cleo Sgouropoulou, Ioannis Voyiatzis, Anastasios Koutoumanos, Said Hamdioui, Peyman Pouyan, M. Comte, Paolo Prinetto, Giuseppe Airo Farulla, Peeter Ellervee, Carlos Delgado Kloos, Raquel M. Crespo Garca
2017ETSScan chain encryption for the test, diagnosis and debug of secure circuits.Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo
2016DATETowards a highly reliable SRAM-based PUFs.Elena-Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
2016IOLTSSTT-MTJ-based TRNG with on-the-fly temperature/current variation compensation.Elena-Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
2016VTSSecurity primitives (PUF and TRNG) with STT-MRAM.Elena-Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto
2015DATESTT MRAM-Based PUFs.Elena-Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto
2015DATERead/write robustness estimation metrics for spin transfer torque (STT) MRAM cell.Elena I. Vatajelu, Rosa Rodrguez-Montas, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015ETSPower-aware voltage tuning for STT-MRAM reliability.Elena I. Vatajelu, Rosa Rodrguez-Montas, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015FPLA portable open-source controller for safe Dynamic Partial Reconfiguration on Xilinx FPGAs.Stefano Di Carlo, Paolo Prinetto, Pascal Trotta, Jan Andersson
2014DATESSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Salvatore Galfano, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Piero Olivo, Davide Bertozzi
2014DSDOn Enhancing Fault Injection's Capabilities and Performances for Safety Critical Systems.Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Frank Reichenbach, Trond Lkstad, Gulzaib Rafiq
2014ETSOn the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial).Marco Indaco, Paolo Prinetto, Elena I. Vatajelu
2014IOLTSA novel methodology to increase fault tolerance in autonomous FPGA-based systems.Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Alessandro Vallero
2013ETSA software-based self test of CUDA Fermi GPUs.Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
2013FPLDependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS.Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
2013FPLFEMIP: A high performance FPGA-based features extractor & matcher for space applications.Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Piergiorgio Lanza
2013IOLTSIncreasing the robustness of CUDA Fermi GPU-based systems.Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
2013IOLTSEfStefano Di Carlo, Salvatore Galfano, Marco Indaco, Paolo Prinetto
2013ITCFault mitigation strategies for CUDA GPUs.Stefano Di Carlo, Giulio Gambardella, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta
2013UICExploring a New Dimension in Code Mobility for Ubiquitous Embedded Systems.Alessandro Cilardo, Nicola Mazzocca, Paolo Prinetto
2012DATEA cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.Cristian Zambelli, Marco Indaco, Michele Fabiano, Stefano Di Carlo, Paolo Prinetto, Piero Olivo, Davide Bertozzi
2012ETSEfficient system-level aging prediction.Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich
2012LRECA platform-independent user-friendly dictionary from Italian to LIS.Umar Shoaib, Nadeem Ahmad, Paolo Prinetto, Gabriele Tiotto
2011ASSETSImproving accessibility for deaf people: an editor for computer assisted translation through virtual avatars.Davide Barberis, Nicola Garazzino, Paolo Prinetto, Gabriele Tiotto
2010ETSMicroprocessor fault-tolerance via on-the-fly partial reconfiguration.Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese
2010ICCHPA Web Based Platform for Sign Language Corpus Creation.Davide Barberis, Nicola Garazzino, Elio Piccolo, Paolo Prinetto, Gabriele Tiotto
2010ITCSystem reliability evaluation using concurrent multi-level simulation of structural faults.Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto
2009DATETest exploration and validation using transaction level models.Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
2009ITCTest infrastructures evaluation at transaction level.Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto
2008ETSApplying March Tests to K-Way Set-Associative Cache Memories.Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino
2008IOLTSReliability in Application Specific Mesh-Based NoC Architectures.Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi
2008ITC"Plug & Test" at System Level via Testable TLM Primitives.Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi
2007IOLTSAnalysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
2006DATEAutomatic march tests generations for static linked faults in SRAMs.Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006DDECSA Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006ETSA 22n March Test for Realistic Static Linked Faults in SRAMs.Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006ETSSingle-Event Upset Analysis and Protection in High Speed Circuits.Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
2005ETSAutomatic March tests generation for static and dynamic faults in SRAMs.Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2005ITCMarch AB, March AB1: new March tests for unlinked dynamic memory faults.Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2005ITCReconfigurable systems self-healing using mobile hardware agents.Alfredo Benso, Alessandro Cilardo, Nicola Mazzocca, Liviu Miclea, Paolo Prinetto, Szilrd Enyedi
2004ITCTowards Microagent based DBIST/DBISR.Liviu Miclea, Szilrd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto
2003IOLTSA Watchdog Processor to Detect Data and Control Flow Errors.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2003IOLTSFAUST: FAUlt-injection Script-based Tool.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, I. Solcia, Luca Tagliaferri
2003ITCData Critically Estimation In Software Applications.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Luca Tagliaferri
2003ITCAgent Based DBIST/DBISR And Its Web/Wireless Management.Liviu Miclea, Szilrd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto
2002DATEBeyond UML to an End-of-Line Functional Test Engine.Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
2002DATEAn Optimal Algorithm for the Automatic Generation of March Tests.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2002IOLTSAutomated Synthesis of SEU Tolerant Architectures from OO Descriptions.Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto
2002ITCEfficient Design of System Test: A Layered Architecture.Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
2002ITCStatic Analysis of SEU Effects on Software Applications.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2001DATESEU effect analysis in an open-source router via a distributed fault injection environment.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2001DATEOn applying the set covering model to reseeding.Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich
2001DATEEmbedded tutorial: TRP: integrating embedded test and ATE.Yervant Zorian, Paolo Prinetto, Joo Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octvio Pscoa Dias, Jorge Semio, Peter Muhmenthaler, W. Radermacher
2001IOLTSValidation of a Software Dependability Tool via Fault Injection Experiments.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Luca Tagliaferri, Paolo Prinetto
2001ITCTowards a unified test process: from UML to end-of-line functional test.Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
2001ITCGRAAL: a tool for highly dependable SRAMs generation.Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Franco Bigongiari
2000DATEOptimal Hardware Pattern Generation for Functional BIST.Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
2000DSNA C/C++ Source-to-Source Compiler for Dependable Applications.Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Luca Tagliaferri
2000ETSAn effective distributed BIST architecture for RAMs.Monica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2000ICCDOn Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs.Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari
2000ICCDAn SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications.Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani
2000IOLTSA Family of Self-Repair SRAM Cores.Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
2000IOLTSA COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT.Alfredo Benso, Silvia Chiusano, Paolo Prinetto
2000ITCHDAlfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian
2000ITCA programmable BIST architecture for clusters of multiple-port SRAMs.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
2000ITCA software development kit for dependable applications in embedded systems.Alfredo Benso, Silvia Chiusano, Paolo Prinetto
2000ITCNon-intrusive BIST for systems-on-a-chip.Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
1999ETSA high-level EDA environment for the automatic insertion of HD-BIST structures.Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
1999ITCHD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs.Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian
1999ITCTesting an MCM for high-energy physics experiments: a case study.Alfredo Benso, Silvia Chiusano, Paolo Prinetto, Simone Giovannetti, Riccardo Mariani, Silvano Motto
1999ITCAn on-line BISTed SRAM IP core.Monica Lobetti Bodoni, Alessio Pricco, Alfredo Benso, Silvia Chiusano, Paolo Prinetto
1999VTSRT-level TPG Exploiting High-Level Synthesis Information.Silvia Chiusano, Fulvio Corno, Paolo Prinetto
1998DATEExploiting Symbolic Techniques for Partial Scan Flip Flop Selection.Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante
1998DATEFast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1998ITCA fault injection environment for microprocessor-based boards.Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1998VTSOn the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits.Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Matteo Sonza Reorda
1998VTSA Test Pattern Generation Methodology for Low-Power Consumption.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997DATEA new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar
1997DATEHybrid symbolic-explicit techniques for the graph coloring problem.Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1997DATENew static compaction techniques of test sequences for sequential circuits.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997ICCDA new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero
1997ICTAIExploiting Symbolic Techniques within Genetic Algorithms for Power Optimization.S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997ITCTestability Analysis and ATPG on Behavioral RT-Level VHDL.Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1997SACSAARA: a simulated annealing algorithm for test pattern generation for digital circuits.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1997VTSHardware Test: Can We Learn from Software Testing?J. Abraham, Phyllis G. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thvenod-Fosse
1997VTSCellular automata for deterministic sequential test pattern generation.Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996DATESelf-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study.Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996DATEAdvanced Techniques for GA-based sequential ATPGs.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, R. Mosca
1996EDCCOn-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore
1996ICTAIA Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits.Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1996ITCComparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996ITCPartial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996PPSNExploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1996VTSScan insertion criteria for low design impact.Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1995DATEProving testing preorders for process algebra descriptions.Fulvio Corno, Marco Cusinato, Mario Ferrero, Paolo Prinetto
1995DATEUsing symbolic techniques to find the maximum clique in very large sparse graphs.Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1995DATEGARDA: a diagnostic ATPG for large synchronous sequential circuits.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1995ITCTesting a Switching Memory in a Telcommunication System.Stefano Barbagallo, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1995VTSImproving topological ATPG with symbolic techniques.Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Glser, Heinrich Theodor Vierhaus
1995VTSA portable ATPG tool for parallel and distributed systems.Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
1994ICTAIGATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits.Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
1994ITCMaking the Circular Self-Test Path Technique Effective for Real Circuits.Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1994ITCAn Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms.Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda
1994VTSA new functional fault model for system-level descriptions.Paolo Camurati, Fulvio Corno, Michela Meo, Paolo Prinetto
1994VTSAn industrial experience in the built-in self test of embedded RAMs.Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina
1992DACA New Model for Improving symbolic Product Machine Traversal.Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda
1992ITCSequential Circuit Diagnosis Based on Formal Verification Techniques.Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
1990CAVThe Use of Model Checking in ATPG for Sequential Circuits.Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda
1990ITCA diagnostic test pattern generation algorithm.Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda
1988ICCDA functional approach to formal hardware verification: the MTI experience.Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto
1988ICCDRandom testability analysis: comparing and evaluating existing approaches.Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
1983DACA new integrated system for PLA testing and verification.Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto
1982MICROMicrocode compaction via microblock definition.Marco Mezzalama, Paolo Prinetto, G. Filippi
1979MICRODesign and implementation of a flexible and interactive microprogram simulator.Marco Mezzalama, Paolo Prinetto