| 2018 | CISIS | A Method of Hardware-Trojan Detection Using Design Verification Techniques. | Yushiro Hiramoto, Satoshi Ohtake |
| 2015 | DDECS | A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model. | Shuichi Sato, Satoshi Ohtake |
| 2015 | PRDC | A Method of Diagnostic Test Generation for Transition Faults. | Renji Ono, Satoshi Ohtake |
| 2013 | CISIS | A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG. | Takanori Moriyasu, Satoshi Ohtake |
| 2011 | ETS | F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
| 2010 | DDECS | A synthesis method to propagate false path information from RTL to gate level. | Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara |
| 2010 | ITC | Constrained ATPG for functional RTL circuits using F-Scan. | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
| 2009 | ASPDAC | Fast false path identification based on functional unsensitizability using RTL information. | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
| 2009 | VTS | A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. | Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara |
| 2007 | ICCAD | Efficient path delay test generation based on stuck-at test generation using checker circuitry. | Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara |
| 2005 | ETS | Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
| 2004 | ETS | A design methodology to realize delay testable controllers using state transition information. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
| 2003 | DATE | A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. | Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara |
| 2002 | VTS | A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. | Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa |
| 2001 | ASPDAC | A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. | Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara |
| 2001 | VLSID | Testable Design of Sequential Circuits with Improved Fault Efficiency. | Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara |
| 2000 | ASPDAC | A non-scan DFT method at register-transfer level to achieve complete fault efficiency. | Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara |