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Seiji Kajihara

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

61

Venues

14

Active years

1993–2022

Best venue rank

A*

Where they publish

Papers

61 indexed papers, newest first.

YearVenueTitleAuthors
2022ITCA Practical Online Error Detection Method for Functional Safety Using Three-Site Implications.Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara
2020IOLTSOn-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test.Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yukiya Miura
2020VTSInnovative Test Practices in Asia.Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama
2019PRDCOn-Chip Delay Measurement for In-Field Test of FPGAs.Yousuke Miyake, Yasuo Sato, Seiji Kajihara
2017ITCAnalysis and mitigation or IR-Drop induced scan shift-errors.Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
2015ETSIdentification of high power consuming areas with gate type and logic level information.Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2014PRDCReduction of NBTI-Induced Degradation on Ring Oscillators in FPGA.Yasuo Sato, Masafumi Monden, Yousuke Miyake, Seiji Kajihara
2013VLSIDOn Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
2012ETSOn-chip temperature and voltage measurement for field testing.Yukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara
2012ITCDART: Dependable VLSI test architecture and its implementation.Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
2012ITCOn pinpoint capture power management in at-speed scan test generation.Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2012VTSA novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara
2011DATETransition-Time-Relation based capture-safety checking for at-speed scan test generation.Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
2011DSNGenetic algorithm based approach for segmented testing.Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato
2011ISLPEDSAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich
2011ITCA novel scan segmentation design method for avoiding shift timing failure in scan testing.Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang
2011VTSPower-aware test generation with guaranteed launch safety for at-speed scan testing.Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor
2010ETSOn estimation of NBTI-Induced delay degradation.Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
2010IOLTSAging test strategy and adaptive test scheduling for SoC failure prediction.Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara
2009ICCADA novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
2009PRDCA GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
2008DDECSDiagnosis of Realistic Defects Based on the X-Fault Model.Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
2008ETSA Capture-Safe Test Generation Scheme for At-Speed Scan Testing.Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2008ICCADEffective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2007DACCritical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
2007ICCADEstimation of delay test quality and its application to test generation.Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2007ITCA novel scheme to reduce power supply noise for high-quality at-speed scan testing.Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
2006ASPDACA dynamic test compaction procedure for high-quality path delay testing.Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006ICCDHighly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
2006ITCA Framework of High-quality Transition Fault ATPG for Scan Circuits.Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006VTSA New ATPG Method for Efficient Capture Power Reduction During Scan Testing.Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
2005ASPDACTest compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
2005ASPDACEvaluation of the statistical delay quality model.Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara
2005DACPath delay test compaction with process variation tolerance.Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2005ITCInvisible delay quality - SDQM model lights up what could not be seen.Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara
2005ITCLow-capture-power test generation for scan-based at-speed testing.Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005VLSIDEfficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan
2005VTSOn Low-Capture-Power Test Generation for Scan Testing.Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2004ETSEnhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values.Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy
2004ICCADOn per-test fault diagnosis using the X-fault model.Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2004VLSIDRandom Access Scan: A solution to test power, test data volume and test time.Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
2003ASPDACOn effective criterion of path selection for delay testing.Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura
2003ICCDA Method to Find Don't Care Values in Test Sequences for Sequential Circuits.Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
2003ICCDOn Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume.Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty
2002ETSOn selecting testable paths in scan designs.Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
2002ICCDDon't-Care Identification on Specific Bits of Test Patterns.Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy
2002ITCOn Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita
2002VTSTest Vector Modification for Power Reduction during Scan Testing.Seiji Kajihara, Koji Ishida, Kohei Miyase
2002VTSOn Test Data Volume Reduction for Multiple Scan Chain Designs.Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
2001ICCADOn Identifying Don't Care Inputs of Test Patterns for Combinational Circuits.Seiji Kajihara, Kohei Miyase
2000ITCSelection of potentially testable path delay faults for test generation.Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy
2000ITCOn validating data hold times for flip-flops in sequential circuits.Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta
1998VLSIDOn Test Pattern Compaction Using Random Pattern Fault Simulation.Seiji Kajihara, Kewal K. Saluja
1997VLSIDA Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
1996VTSOn the effects of test compaction on defect coverage.Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara
1995VTSCompact test generation for bridging faults under IRemata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara
1995VTSResynthesis for sequential circuits designed with a specified initial state.Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita
1994ITCReduced Scan Shift: A New Testing Method for Sequential Circuit.Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita
1994VTSOn compacting test sets by addition and removal of test vectors.Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1993DACCost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits.Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy
1993ICCADTest generation for multiple faults based on parallel vector pair analysis.Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita