| 2025 | RSP | A Prototyping Framework for P4-Programmable Traffic Managers. | Karl La Grassa, Andr Bliveau, Mathieu Lonardon, Jean-Pierre David, Matthieu Arzel, Yvon Savaria |
| 2024 | ACSSC | Sharpness-Aware Minimization Scaled by Outlier Normalization for Robust DNNs on In-Memory Computing Accelerators. | Sbastien Henwood, Gonalo Mordido, Yvon Savaria, Sarath Chandar, Franois Leduc-Primeau |
| 2024 | ISCAS | Utilization of Noise-Shaping in Mixed-Signal Timing-Skew Mismatch Calibration of TI-ADCs. | Hamidreza Mafi, Mohamed Amine Bensenouci, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Yvon Savaria |
| 2024 | NetSoft | Enhancing P4 Syntax to Support Extended Finite State Machines as Native Stateful Objects. | Florent Allard, Tarek Ould-Bachir, Yvon Savaria |
| 2023 | ASPDAC | BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. | Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David |
| 2023 | ISCAS | Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. | MohammadHossein AskariHemmat, Tho Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Grkaynak, Luca Benini, Franois Leduc-Primeau, Yvon Savaria, Jean-Pierre David |
| 2023 | ISCAS | An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs. | Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria |
| 2022 | ISCAS | A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. | Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria |
| 2022 | ISCAS | Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. | Julien Posso, Guy Bois, Yvon Savaria |
| 2022 | ISCAS | An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. | Mengyue Su, Jean-Pierre David, Yvon Savaria, Bill Pontikakis, Thomas Luinaud |
| 2021 | FPGA | Design Principles for Packet Deparsers on FPGAs. | Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria |
| 2021 | ISCAS | Causal Information Prediction for Analog Circuit Design Using Variable Selection Methods Based on Machine Learning. | Ahmed Abuelnasr, Mostafa Amer, Ahmed Ragab, Benoit Gosselin, Yvon Savaria |
| 2021 | ISCAS | Design and Analysis of Combined Input-Voltage Feedforward and PI Controllers for the Buck Converter. | Mostafa Amer, Ahmed Abuelnasr, Ahmed Ragab, Ahmad Hassan, Mohamed Ali, Benoit Gosselin, Mohamad Sawan, Yvon Savaria |
| 2021 | ISCAS | RISC-V Barrel Processor for Deep Neural Network Acceleration. | MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David |
| 2021 | ISCAS | Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. | Hachem Bensalem, Yves Blaquire, Yvon Savaria |
| 2020 | FCCM | RISC-V Barrel Processor for Accelerator Control. | MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David |
| 2020 | FPGA | Unleashing the Power of FPGAs as Programmable Switches. | Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois |
| 2020 | HPSR | Bridging the Gap: FPGAs as Programmable Switches. | Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois |
| 2020 | ISCAS | Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers. | Ahmed Abuelnasr, Mohamed Ali, Mostafa Amer, Morteza Nabavi, Ahmad Hassan, Benoit Gosselin, Yvon Savaria |
| 2020 | ISCAS | OTA-Free MASH 2-2 Noise Shaping SAR ADC: System and Design Considerations. | Masoume Akbari, Mohammad Honarparvar, Yvon Savaria, Mohamad Sawan |
| 2020 | ISCAS | Analog Circuits to Accelerate the Relaxation Process in the Equilibrium Propagation Algorithm. | Armin Najarpour Foroushani, Hussein Assaf, Fereidoon Hashemi Noshahr, Yvon Savaria, Mohamad Sawan |
| 2020 | VTC | Indoor Localization Using Channel State Information With Regression Artificial Neural Networks. | Seyed Mohsen Samadani, Yvon Savaria, Chah Nerguizian |
| 2019 | ISCAS | Toward In-System Monitoring of OpenCL-Based Designs on FPGA. | Hachem Bensalem, Yves Blaquire, Yvon Savaria |
| 2019 | ISCAS | A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. | Maryem Benyoussef, Claude Thibeault, Yvon Savaria |
| 2019 | ISCAS | Bit-Slicing FPGA Accelerator for Quantized Neural Networks. | Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David |
| 2019 | MICCAI | U-Net Fixed-Point Quantization for Medical Image Segmentation. | MohammadHossein AskariHemmat, Sina Honari, Lucas Rouhier, Christian S. Perone, Julien Cohen-Adad, Yvon Savaria, Jean-Pierre David |
| 2018 | CCGRID | A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. | Thibaut Stimpfling, J. M. Pierre Langlois, Normand Blanger, Yvon Savaria |
| 2018 | ISCAS | High-Temperature Modeling of the I-V Characteristics of GaN150 HEMT Using Machine Learning Techniques. | Ahmed Abubakr, Ahmad Hassan, Ahmed Ragab, Soumaya Yacout, Yvon Savaria, Mohamad Sawan |
| 2018 | ISCAS | High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT. | Mostafa Amer, Ahmad Hassan, Ahmed Ragab, Soumaya Yacout, Yvon Savaria, Mohamad Sawan |
| 2018 | ISCAS | Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. | Imad Benacer, Franois-Raymond Boyer, Yvon Savaria |
| 2018 | ISCAS | Implementation of a Cache-Based IPv6 Lookup System with Hashing. | Bachir Fradj, Benjamin Wolff, Normand Blanger, Yvon Savaria |
| 2018 | ISCAS | Custom Low Power Processor for Polar Decoding. | Mathieu Lonardon, Camille Leroux, David Binet, J. M. Pierre Langlois, Christophe Jgo, Yvon Savaria |
| 2018 | ISCAS | A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications. | Seyed Mohammad Noghabaei, Rafael L. Radin, Yvon Savaria, Mohamad Sawan |
| 2018 | VTS | Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. | Omar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria, Claude Thibeault |
| 2017 | FPGA | An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). | Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois |
| 2017 | IOLTS | Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT. | Ghaith Bany Hamad, Ghaith Kazma, Otmane At Mohamed, Yvon Savaria |
| 2017 | ISCAS | A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. | Safa Berrima, Yves Blaquire, Yvon Savaria |
| 2017 | ISCAS | Scalable memory-less architecture for string matching with FPGAs. | Ideh Sarbishei, Shervin Vakili, J. M. Pierre Langlois, Yvon Savaria |
| 2017 | ISORC | A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications. | Michel Gemieux, Yvon Savaria, Jean-Pierre David, Guchuan Zhu |
| 2016 | FDL | Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking. | Marwan Ammar, Ghaith Bany Hamad, Otmane At Mohamed, Yvon Savaria |
| 2016 | FDL | Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients. | Ghaith Bany Hamad, Ghaith Kazma, Otmane At Mohamed, Yvon Savaria |
| 2016 | ICCAD | Efficient and accurate analysis of single event transients propagation using SMT-based techniques. | Ghaith Bany Hamad, Ghaith Kazma, Otmane At Mohamed, Yvon Savaria |
| 2016 | ISCAS | A practical design method for prototyping self-timed processors using FPGAs. | Mickal Fiorentino, Yvon Savaria, Claude Thibeault, Pascal Gervais |
| 2016 | ISCAS | Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL. | Ghaith Bany Hamad, Otmane At Mohamed, Yvon Savaria |
| 2016 | ISCAS | Wireless power transfer through metallic barriers enclosing a harsh environment; feasibility and preliminary results. | Ahmad Hassan, Aref Trigui, Umar Shafique, Yvon Savaria, Mohamad Sawan |
| 2016 | ISCAS | A compact spatially configurable differential input stage for a field programmable interconnection network. | Wasim Hussain, Yvon Savaria, Yves Blaquire |
| 2016 | ISCAS | Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC. | Mounir Khelifi, Daniel Massicotte, Yvon Savaria |
| 2016 | VTS | WeSPer: A flexible small delay defect quality metric. | Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault |
| 2015 | DATE | Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking. | Khaza Anuarul Hoque, Otmane At Mohamed, Yvon Savaria |
| 2015 | IOLTS | Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients. | Ghaith Bany Hamad, Otmane At Mohamed, Yvon Savaria |
| 2015 | IOLTS | Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit. | Gontran Sion, Yves Blaquire, Yvon Savaria |
| 2015 | ISCAS | Modeling the faulty behaviour of digital designs using a feed forward neural network approach. | Zeynab Mirzadeh, Jean-Franois Boland, Yvon Savaria |
| 2015 | ISCAS | Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. | Pascal Nsame, Guy Bois, Yvon Savaria |
| 2014 | ICFHR | Neuromuscular Representation and Synthetic Generation of Handwritten Whiteboard Notes. | Andreas Fischer, Rjean Plamondon, Christian O'Reilly, Yvon Savaria |
| 2014 | ISCAS | Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain. | Yves Blaquire, Yan Basile-Bellavance, Safa Berrima, Yvon Savaria |
| 2014 | ISCAS | Abstracting Single Event Transient characteristics variations due to input patterns and fan-out. | Ghaith Bany Hamad, Syed Rafay Hasan, Otmane At Mohamed, Yvon Savaria |
| 2014 | MEMOCODE | Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. | Khaza Anuarul Hoque, Otmane At Mohamed, Yvon Savaria, Claude Thibeault |
| 2014 | SSPR | A Hausdorff Heuristic for Efficient Computation of Graph Edit Distance. | Andreas Fischer, Rjean Plamondon, Yvon Savaria, Kaspar Riesen, Horst Bunke |
| 2013 | HPDC | Optimal packet classification applicable tothe OpenFlow context. | Thibaut Stimpfling, Yvon Savaria, Andr Bliveau, Normand Blanger, Omar Cherkaoui |
| 2013 | ISCAS | An interface for the I | Wasim Hussain, Yvon Savaria, Yves Blaquire |
| 2012 | ISCAS | Two-level configuration for FPGA: A new design methodology based on a computing fabric. | Mathieu Allard, Patrick Grogan, Yvon Savaria, Jean-Pierre David |
| 2012 | ISCAS | Identification of soft error glitch-propagation paths: Leveraging SAT solvers. | Ghaith Bany Hamad, Otmane At Mohamed, Syed Rafay Hasan, Yvon Savaria |
| 2012 | ISCAS | Propagating analog signals through a fully digital network on an electronic system prototyping platform. | Omar Al-Terkawi Hasib, Walder Andre, Yves Blaquire, Yvon Savaria |
| 2012 | RSP | A new approach for pin detection for an electronic system prototyping reconfigurable platform. | Hai H. Nguyen, Mikael Guillemot, Yvon Savaria, Yves Blaquire |
| 2011 | ISCAS | Comparative analysis of contrast enhancement algorithms in surveillance imaging. | Diana Carolina Gil, Rana Farah, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau, Yvon Savaria |
| 2010 | ISCAS | Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter. | Omar Al-Terkawi Hasib, Mohamad Sawan, Yvon Savaria |
| 2010 | ISCAS | An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
| 2009 | ISCAS | An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs). | Syed Rafay Hasan, Bill Pontikakis, Yvon Savaria |
| 2009 | ISCAS | Workflow for an Electronic Configurable Prototyping System. | Etienne Lepercq, Yves Blaquire, Richard Norman, Yvon Savaria |
| 2008 | ISCAS | Modeling and simulation of complex heterogeneous systems. | Amine Anane, El Mostapha Aboulhamid, Julie Vachon, Yvon Savaria |
| 2007 | ISCAS | Modeling the Substrate Noise Injected by a DC-DC Converter. | Vincent Binet, Yvon Savaria, Michel Meunier, Yves Gagnon |
| 2007 | ISCAS | High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique. | Robert Chebli, Mohamad Sawan, Yvon Savaria, Kamal El-Sankary |
| 2007 | ISCAS | Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. | Syed Rafay Hasan, Yvon Savaria |
| 2007 | ISCAS | A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. | Bill Pontikakis, Hung Tien Bui, Franois R. Boyer, Yvon Savaria |
| 2007 | ISCAS | Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier. | Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria |
| 2006 | DATE | Soft-error classification and impact analysis on real-time operating systems. | N. Ignat, Bogdan Nicolescu, Yvon Savaria, Gabriela Nicolescu |
| 2006 | ISCAS | Architecture of a hypertransport tunnel. | Ami Castonguay, Yvon Savaria |
| 2006 | ISCAS | A power planning model for implantable stimulators. | Saeid Hashemi, Mohamad Sawan, Yvon Savaria |
| 2006 | ISCAS | High-voltage operational amplifier based on dual floating-gate transistors. | Z. Huang, Yvon Savaria, Mohamad Sawan, R. Meinga |
| 2006 | ISCAS | Design exploration with an application-specific instruction-set processor for ELA deinterlacing. | Maria Mbaye, D. Lebel, Normand Blanger, Yvon Savaria, Samuel Pierre |
| 2006 | ISCAS | A novel 2-GHz band-pass delta modulator dedicated to wireless receivers. | Ali Naderi, Mohamad Sawan, Yvon Savaria |
| 2006 | ISCAS | A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. | Bill Pontikakis, Franois R. Boyer, Yvon Savaria |
| 2006 | ISCAS | Zero skew differential clock distribution network. | Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria |
| 2005 | DATE | The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application. | Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid |
| 2005 | ISCAS | Parameters estimation applied to automatic video processing algorithms validation. | S. Catudal, Marc-Andr Cantin, Yvon Savaria |
| 2005 | ISCAS | A novel approach for implementing ultra-high speed flash ADC using MCML circuits. | Dinh Hung Dang, Yvon Savaria, Mohamad Sawan |
| 2005 | ISCAS | Implementation of a cycle by cycle variable speed processor. | H. G. Epassa, Franois R. Boyer, Yvon Savaria |
| 2005 | ISCAS | A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. | Alexandre Landry, Mohamed Nekili, Yvon Savaria |
| 2005 | ISCAS | . A new switch compensation technique for inverted R-2R ladder DACs. | David Marche, Yves Gagnon, Yvon Savaria |
| 2005 | ISCAS | Application specific instruction-set processor generation for video processing based on loop optimization. | Maria Mbaye, Normand Blanger, Yvon Savaria, Samuel Pierre |
| 2005 | ISCAS | Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. | G. Provost, Marc-Andr Cantin, Mohamad Sawan, Christian Cardinal, Yvon Savaria, David Haccoun |
| 2005 | ISCAS | Design methods for CMOS low-current finely tunable voltage references covering a wide output range. | Simon Rioux, Alain Lacourse, Yvon Savaria, Michel Meunier |
| 2005 | ISCAS | A complete spurs distribution model for direct digital period synthesizers. | Max-Elie Salomon, Abdelhakim Khouas, Yvon Savaria |
| 2005 | ISCAS | Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator. | Guillaume Wild, Yvon Savaria, Michel Meunier |
| 2005 | RSP | A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC. | Ami Castonguay, Yvon Savaria |
| 2004 | IOLTS | Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. | Bogdan Nicolescu, Yvon Savaria, Raoul Velazco |
| 2004 | ISCAS | Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. | Hung Tien Bui, Yvon Savaria |
| 2004 | ISCAS | An ADPLL circuit using a DDPS for genlock applications. | Dorin Emil Calbaza, Ioan Cordos, Nigel Seth-Smith, Yvon Savaria |
| 2004 | ISCAS | An on-chip delay measurements module for nanostructures characterization. | Olivier Duval, Yvon Savaria |
| 2004 | ISCAS | Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. | Badre Izouggaghen, Abdelhakim Khouas, Yvon Savaria |
| 2004 | ISCAS | Assertion-based on-line verification and debug environment for complex hardware systems. | Kevin Peterson, Yvon Savaria |
| 2003 | ISCAS | A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. | Mathieu Renaud, Yvon Savaria |
| 2003 | ISCAS | A new memory reference reduction method for FFT implementation on DSP. | Yiyan Tang, Lie Qian, Yuke Wang, Yvon Savaria |
| 2002 | FPGA | A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. | J. Dido, N. Graudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier |
| 2002 | ISCAS | Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique. | A. Bendali, Yvon Savaria |
| 2002 | ISCAS | A CMOS phase-locked loop with an auto-calibrated VCO. | Youcef Fouzar, Yvon Savaria, Mohamad Sawan |
| 2002 | ISCAS | Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm. | L.-P. Lafrance, Marc-Andr Cantin, Yvon Savaria, S. H. Sung, Pierre Lavoie |
| 2002 | ISCAS | A linear phase detector for arbitrary clock signals. | Mathieu Renaud, Yvon Savaria |
| 2002 | MVA | FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders. | Hakim Khali, Yvon Savaria |
| 2001 | ICCD | Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. | Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria |
| 2001 | ISCAS | An automatic word length determination method. | Marc-Andr Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie |
| 2001 | ISCAS | A new controlled gain phase-locked loop technique. | Youcef Fouzar, Yvon Savaria, Mohamad Sawan |
| 2001 | ISCAS | Minimizing process-induced skew using delay tuning. | Mohamed Nekili, Yvon Savaria, Guy Bois |
| 2001 | ISCAS | Performance estimators for hardware/software co-design. | Lvis Thriault, Daniel Audet, Yvon Savaria |
| 2001 | VTS | Tools for the Characterization of Bipolar CML Testability. | Ginette Mont, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst |
| 2000 | ISCAS | Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. | Marc-Andr Cantin, Yves Blaquire, Yvon Savaria, Pierre Lavoie, Eric Granger |
| 2000 | ISCAS | A new fully integrated CMOS phase-locked loop with low jitter and fast lock time. | Youcef Fouzar, Mohamad Sawan, Yvon Savaria |
| 2000 | ISCAS | A methodology for validating digital circuits with mutation testing. | Patrice Vado, Yvon Savaria, Yannick Zoccarato, Chantal Robach |
| 1999 | DATE | Design For Testability Method for CML Digital Circuits. | Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham |
| 1999 | FCCM | Design of a JTAG Based Run Time Reconfigurable System. | Cynthia Cousineau, Franois Laperle, Yvon Savaria |
| 1999 | ISCAS | Jitter model of direct digital synthesis clock generators. | Dorin Emil Calbaza, Yvon Savaria |
| 1999 | ISCAS | Development of a high performance TSPC library for implementation of large digital building blocks. | B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois |
| 1999 | ISCAS | A new approach to analyze interconnect delays in RC wire models. | Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria, Pierre Garon |
| 1998 | FCCM | A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing. | Pascal Poir, Marc-Andr Cantin, Herv Daniel, Yves Blaquire, Yvon Savaria |
| 1998 | ICCD | Optimal design of synchronous circuits using software pipelining techniques. | Franois R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Imed Eddine Bennour |
| 1998 | ICCD | Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications. | Paul Marriott, Ivan C. Kraljic, Yvon Savaria |
| 1996 | VTS | Design and performance of CMOS TSPC cells for high speed pseudo random testing. | Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska |
| 1995 | ISCAS | On Using Partial Reset for Pseudo-Random Testing. | Mohamed Soufi, Yvon Savaria, Bozena Kaminska |
| 1995 | VTS | On the design of at-speed testable VLSI circuits. | Mohamed Soufi, Yvon Savaria, Bozena Kaminska |
| 1994 | ISCAS | Fast Convergence with Low Precision Weights in ART1 Networks. | Jean-Franois Crespo, Pierre Lavoie, Yvon Savaria |
| 1994 | ISCAS | A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. | Sameh Ghannoum, Dmitri Chtchvyrkov, Yvon Savaria |
| 1994 | ISCAS | Pseudo-Random Vector Compaction for Sequential Testability. | Naim Ben-Hamida, Bozena Kaminska, Yvon Savaria |
| 1994 | ISCAS | A Fast Low-Power Driver for Long Interconnections in VLSI Systems. | Mohamed Nekili, Yvon Savaria, Guy Bois |
| 1994 | ISCAS | A Fast CMOS Voltage-Controlled Ring Oscillator. | Yvon Savaria, Dmitri Chtchvyrkov, John F. Currie |
| 1993 | ISCAS | Initiability: A Measure of Sequential Testability. | Naim Ben-Hamida, Bozena Kaminska, Yvon Savaria |
| 1993 | ISCAS | A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm. | Hakim Khali, Jean-Louis Houle, Yvon Savaria |
| 1993 | ISCAS | Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. | Mohamed Nekili, Yvon Savaria |
| 1989 | ITC | Design-for-Testability Using Test Design Yield and Decision Theory. | Bozena Kaminska, Yvon Savaria |
| 1989 | ITC | A Pragmatic Approach to the Design of Self-Testing Circuits. | Yvon Savaria, Bruno Lagu, Bozena Kaminska |
| 1984 | ITC | A Design for Machines with Built-In Tolerance to Soft Errors. | Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes |