| 2012 | OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters. | Daniel Arbet, Gbor Gyepes, Juraj Brenkus, Viera Stopjakov |
| 2012 | Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifier. | Ahmed Naif M. Alahmadi, Gordon Russell, Alex Yakovlev |
| 2011 | Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2011 | Abstract modeling and simulation based selective estimation. | Yaseen Zaidi, Sumit Adhikari, Christoph Grimm |
| 2011 | Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip. | Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen |
| 2011 | An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platform. | Wlodzimierz Wrona, Pawel Duc, Lukasz Barcik, Wojciech Pietrasina |
| 2011 | Behavioral model of TRNG based on oscillator rings implemented in FPGA. | Knut Wold, Slobodan Petrovic |
| 2011 | A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring. | Martin Wirnshofer, Leonhard Hei, Georg Georgakos, Doris Schmitt-Landsiedel |
| 2011 | Statistical analysis of 6T SRAM data retention voltage under process variation. | Elena-Ioana Vatajelu, Joan Figueras |
| 2011 | A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors. | Markus Ulbricht, Mario Schlzel, Tobias Koal, Heinrich Theodor Vierhaus |
| 2011 | Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders. | Xuan-Tu Tran, Van-Huan Tran |
| 2011 | A study of path delay variations in the presence of uncorrelated power and ground supply noise. | Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2011 | Effective hash-based IPv6 longest prefix match. | Jiri Tobola, Jan Korenek |
| 2011 | SiGe BiCMOS platform - baseline technology for More Than Moore process module integration. | Bernd Tillack |
| 2011 | Stacking order impact on overall 3D die-to-wafer Stacked-IC cost. | Mottaqiallah Taouil, Said Hamdioui |
| 2011 | Communication modelling and synthesis for NoC-based systems with real-time constraints. | Mihkel Tagel, Peeter Ellervee, Thorsten Hollstein, Gert Jervan |
| 2011 | Cost effective scaling to 22nm and below technology nodes. | Andrzej J. Strojwas |
| 2011 | Advanced fault tolerant bus for multicore system implemented in FPGA. | Martin Straka, Jan Kastil, Jaroslav Novotn, Zdenek Kotsek |
| 2011 | Fault injection analysis of transient faults in clustered VLIW processors. | Luca Sterpone, Davide Sabena, Salvatore Campagna, Matteo Sonza Reorda |
| 2011 | Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC. | Oliver Stecklina, Frank Vater, Thomas Basmer, Erik Bergmann, Hannes Menzel |
| 2011 | Automatic property generation for the formal verification of bus bridges. | Mathias Soeken, Ulrich Khne, Martin Freibothe, Grschwin Fey, Rolf Drechsler |
| 2011 | High-performance hardware accelerators for sorting and managing priorities. | Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson |
| 2011 | CAD tool for PLL Design. | Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz |
| 2011 | PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. | Krzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz |
| 2011 | Low-complexity integrated circuit aging monitor. | Aleksandar Simevski, Rolf Kraemer, Milos Krstic |