| 2012 | Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST. | M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi |
| 2012 | Application of IDDT test towards increasing SRAM reliability in nanometer technologies. | Gbor Gyepes, Daniel Arbet, Juraj Brenkus, Viera Stopjakov |
| 2012 | On the use of assertions for embedded-software dynamic verification. | Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli |
| 2012 | HLS-DoNoC: High-level simulator for dynamically organizational NoCs. | Liang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho, Hannu Tenhunen |
| 2012 | Asynchronous circuit design: From basics to practical applications. | Eckhard Grass, Milos Krstic, Xin Fan, Steffen Zeidler |
| 2012 | Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology. | Jacek Gradzki |
| 2012 | Automatic integration of hardware descriptions into system-level models. | Ralph Grgen, Jan-Hendrik Oetjens, Wolfgang Nebel |
| 2012 | Multisine signal generation method for a bioimpedance measurement device. | Maksim Gorev, Vadim Pesonen, Peeter Ellervee |
| 2012 | Temperature and on-chip crosstalk measurement using ring oscillators in FPGA. | Martin Gag, Tim Wegner, Ansgar Waschki, Dirk Timmermann |
| 2012 | Test and configuration architecture of a sub-THz CMOS detector array. | Pter Fldesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Krolyi |
| 2012 | Improving the iterative power of resynthesis. | Petr Fiser, Jan Schmidt |
| 2012 | A 1V, low power, high-gain, 3 - 11 GHz double-balanced CMOS sub-harmonic mixer. | Rouhollah Feghhi, Sasan Naseh |
| 2012 | A new SAT-based ATPG for generating highly compacted test sets. | Stephan Eggersgl, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler |
| 2012 | Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification. | Emad Samuel Malki Ebeid, Davide Quaglia, Franco Fummi |
| 2012 | Genetic method for compressed skewed-load delay test generation. | Roland Dobai, Marcel Balz |
| 2012 | Automated debugging from pre-silicon to post-silicon. | Mehdi Dehbashi, Grschwin Fey |
| 2012 | On test time reduction using pattern overlapping, broadcasting and on-chip decompression. | Martin Chloupek, Ondrej Novk, Jiri Jencek |
| 2012 | Auto-calibration techniques in built-in jitter measurement circuit. | Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng |
| 2012 | On-chip aging sensor to monitor NBTI effect in nano-scale SRAM. | Arthur Ceratti, Thiago Copetti, Letcia Maria Bolzani Poehls, Fabian Vargas |
| 2012 | Synthesis of Petri nets into FPGA with operation flexible memories. | Arkadiusz Bukowiec, Marian Adamski |
| 2012 | A low-overhead monitoring ring interconnect for MPSoC parameter optimization. | Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf |
| 2012 | A SBST strategy to test microprocessors' Branch Target Buffer. | Paolo Bernardi, Lyl M. Ciganda, Michelangelo Grosso, Ernesto Snchez, Matteo Sonza Reorda |
| 2012 | CDMA technique for Network-on-Chip. | Ahmed A. El Badry, Mohamed A. Abd El-Ghany |
| 2012 | CIVA: Custom instruction vulnerability analysis framework. | Ali Azarpeyvand, Mostafa E. Salehi, Seid Mehdi Fakhraie |
| 2012 | Low power scan by partitioning and scan hold. | Efi Arvaniti, Yiorgos Tsiatouhas |