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International Symposium on Design and Diagnostics of Electronic Circuits and Systems

DDECS

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering

Papers indexed

1,124

2006–2026

Papers per year

200691 peak2026

DDECS papers

1,124 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2006An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories.Mario Garca-Valderas, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena-Arrontes
2006Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka
2006A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming.Zbysek Gajda
2006Multiple-Vector Column-Matching BIST Design Method.Petr Fiser, Hana Kubtov
2006A Modified Debugging Infrastructure to Assist Real Time Fault Injection Campaigns.Andr V. Fidalgo, Gustavo R. Alves, Jos M. Ferreira
2006Probabilistic Testability Analysis and DFT Methods at RTL.Jos M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, Joo Paulo Teixeira
2006A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology.Flix Tobajas, Roberto Esper-Chan, Ral Regidor, Octavio Santana, Roberto Sarmiento
2006PE-ICE: Parallelized Encryption and Integrity Checking Engine.Reouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet
2006Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.Jochen Eisinger, Ilia Polian, Bernd Becker, Alexander Metzner, Stephan Thesing, Reinhard Wilhelm
2006A System for Transforming an ANSI C Code with OpenMP Directives into a SystemC Description.Piotr Dziurzanski, Wlodzimierz Bielecki, Konrad Trifunovic, M. Kleszczonek
2006March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006A Switch Supporting Circuit and Packet Switching for On-Chip Networks.Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu
2006Comparing Subtraction-Free and Traditional AMI.Jir Bucek, Rbert Lrencz
2006A Leakage-based Random Bit Generator with On-line Fault Detection.Marco Bucci, Raimondo Luzzi
2006Die Attach Quality Testing by Fully Contact-less Measurement Method.Gyrgy Bognr, Gyula Horvth, Zoltn Szucs, Vladimr Szkely
2006Concurrent Testing of Digital Circuits for Advanced Fault Models.Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar
2006Test Considerations about the Structured ASIC Paradigm.Paolo Bernardi, Michelangelo Grosso
2006A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006ISA Based Functional Test Generation with Application to Self-Test of RISC Processors.V. V. Belkin, S. G. Sharshunov
2006A Sinewave Analyzer for Mixed-Signal BIST Applications in a 0.35m Technology.Manuel J. Barragan Asian, Diego Vzquez, Adoracin Rueda
2006Lissajous Based Mixed-Signal Testing for N-Observable Signals.Luz Balado, Emili Lupon, L. Garca, Rosa Rodrguez-Montas, Joan Figueras
2006Low Level Bus Traffic Replay for the Test and Debugging of Time-Triggered Communication Systems.Eric Armengaud
2006Parallel Memory Architecture for Arbitrary Stride Accesses.Eero Aho, Jarno Vanne, Timo D. Hmlinen
2006Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow.Mohamed Abbas, Makoto Ikeda, Kunihiro Asada
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