| 2011 | A Robust Metric for Screening Outliers from Analogue Product Manufacturing Tests Responses. | Shaji Krishnan, Hans G. Kerkhoff |
| 2011 | Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs. | Esa Korhonen, Juha Kostamovaara |
| 2011 | Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation. | Sehun Kook, Aritra Banerjee, Abhijit Chatterjee |
| 2011 | Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links. | Anelise Kologeski, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt |
| 2011 | Improved DFT for Testing Power Switches. | S. Saqib Khursheed, Sheng Yang, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn |
| 2011 | Optimization of Assertion Placement in Time-Constrained Embedded Systems. | Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita |
| 2011 | Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs. | Sandra Irobi, Zaid Al-Ars, Said Hamdioui |
| 2011 | A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. | Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai |
| 2011 | Enhancement of Clock Delay Faults Testing. | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
| 2011 | Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS. | Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Rick Wong, Shi-Jie Wen |
| 2011 | Latency Analysis for Sequential Circuits. | Alexander Finder, Andr Slflow, Grschwin Fey |
| 2011 | Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures. | Hongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty |
| 2011 | Scan Attacks and Countermeasures in Presence of Scan Response Compactors. | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
| 2011 | Structural Test for Graceful Degradation of NoC Switches. | Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich |
| 2011 | Reduced ATE Interface for High Test Data Compression. | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2011 | Structural In-Field Diagnosis for Random Logic Circuits. | Alejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein |
| 2011 | Revisiting Application-Dependent Test for FPGA Devices. | Alessandro Cilardo, Carmelo Lofiego, Antonino Mazzeo, Nicola Mazzocca |
| 2011 | DfT Architecture for 3D-SICs with Multiple Towers. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | Online Univariate Outlier Detection in Final Test: A Robust Rolling Horizon Approach. | Harm C. M. Bossers, Johann L. Hurink, Gerard J. M. Smit |
| 2011 | Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction. | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
| 2011 | Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. | Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer |
| 2011 | Critical Fault-Based Pattern Generation for Screening SDDs. | Fang Bao, Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, LeRoy Winemberg, Mohammad Tehranipoor |
| 2011 | Power Aware Post-manufacture Tuning of Analog Nanocircuits. | Aritra Banerjee, Subho Chatterjee, Azad Naeemi, Abhijit Chatterjee |
| 2011 | Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. | Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar |
| 2010 | New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. | Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen |