Skip to content

Hans-Joachim Wunderlich

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

163

Venues

16

Active years

1985–2026

Best venue rank

A*

Where they publish

Papers

163 indexed papers, newest first.

YearVenueTitleAuthors
2026DDECSReliability Assessment in Approximate Accelerator Synthesis.Somayeh Sadeghi Kohan, Muhammad Awais, Qazi Arbab Ahmed, Marco Platzner, Sybille Hellebrand, Thorsten Jungeblut, Hans-Joachim Wunderlich
2025ETSRobust Pattern Generation for Small Delay Faults under the Impact of Variations.Hanieh Jafarzadeh, Sybille Hellebrand, Hans-Joachim Wunderlich
2025ETSEuropean Test Symposium Teams: an Anniversary Snapshot.Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilrd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersgl, Grschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard, Marcello Traiola, Arnaud Virazel, Fernando Fernandes dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letcia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, Fabian Luis Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2024ETSTime and Space Optimized Storage-based BIST under Multiple Voltages and Variations.Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich
2024ITCMinimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing.Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich
2023DATERobust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection.Zahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch, Hans-Joachim Wunderlich
2023DSNLow Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.Somayeh Sadeghi Kohan, Sybille Hellebrand, Hans-Joachim Wunderlich
2023DSNGuardband Optimization for the Preconditioned Conjugate Gradient Algorithm.Natalia Lylina, Stefan Holst, Hanieh Jafarzadeh, Alexandra Kourfali, Hans-Joachim Wunderlich
2023ETSSynthesis of IJTAG Networks for Multi-Power Domain Systems on Chips.Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler
2023IOLTSExploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization.Natalia Lylina, Stefan Holst, Hanieh Jafarzadeh, Alexandra Kourfali, Hans-Joachim Wunderlich
2023ITCRobust Pattern Generation for Small Delay Faults Under Process Variations.Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich
2022DATEIntelligent Methods for Test and Reliability.Hussam Amrouch, Jens Anders, Steffen Becker, Maik Betka, Gerd Bleher, Peter Domanski, Nourhan Elhamawy, Thomas Ertl, Athanasios Gatzastras, Paul R. Genssler, Sebastian Hasler, Martin Heinrich, Andr van Hoorn, Hanieh Jafarzadeh, Ingmar Kallfass, Florian Klemme, Steffen Koch, Ralf Ksters, Andrs Lalama, Raphal Latty, Yiwen Liao, Natalia Lylina, Zahra Paria Najafi-Haghi, Dirk Pflger, Ilia Polian, Jochen Rivoir, Matthias Sauer, Denis Schwachhofer, Steffen Templin, Christian Volmer, Stefan Wagner, Daniel Weiskopf, Hans-Joachim Wunderlich, Bin Yang, Martin Zimmermann
2022DATERobust Reconfigurable Scan Networks.Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich
2022ETSOn Extracting Reliability Information from Speed Binning.Zahra Paria Najafi-Haghi, Florian Klemme, Hussam Amrouch, Hans-Joachim Wunderlich
2022ITCEfficient and Robust Resistive Open Defect Detection Based on Unsupervised Deep Learning.Yiwen Liao, Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich, Bin Yang
2021IOLTSConcurrent Test of Reconfigurable Scan Networks for Self-Aware Systems.Chih-Hao Wang, Natalia Lylina, Ahmed Atteya, Tong-Yu Hsieh, Hans-Joachim Wunderlich
2021ITCTestability-Enhancing Resynthesis of Reconfigurable Scan Networks.Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich
2021VTSA Hybrid Protection Scheme for Reconfigurable Scan Networks.Natalia Lylina, Ahmed Atteya, Hans-Joachim Wunderlich
2020DATEUsing Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction.Chang Liu, Eric Schneider, Hans-Joachim Wunderlich
2020DATESynthesis of Fault-Tolerant Reconfigurable Scan Networks.Sebastian Brandhofer, Michael A. Kochte, Hans-Joachim Wunderlich
2020DATEGPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling.Eric Schneider, Hans-Joachim Wunderlich
2020ETSVariation-Aware Defect Characterization at Cell Level.Zahra Paria Najafi-Haghi, Marzieh Hashemipour-Nazari, Hans-Joachim Wunderlich
2020ITCLogic Fault Diagnosis of Hidden Delay Defects.Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen
2020ITCSecurity Preserving Integration and Resynthesis of Reconfigurable Scan Networks.Natalia Lylina, Ahmed Atteya, Chih-Hao Wang, Hans-Joachim Wunderlich
2020VTSSwitch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling.Eric Schneider, Hans-Joachim Wunderlich
2019DATEOn Secure Data Flow in Reconfigurable Scan Networks.Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Lylina, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
2019ITCVariation-Aware Small Delay Fault Diagnosis on Compressed Test Responses.Stefan Holst, Eric Schneider, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich
2019ITCSecurity Compliance Analysis of Reconfigurable Scan Networks.Natalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2018ASPDACMulti-level timing simulation on GPUs.Eric Schneider, Michael A. Kochte, Hans-Joachim Wunderlich
2018ETSOnline prevention of security violations in reconfigurable scan networks.Ahmed Atteya, Michael A. Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
2018ETSDevice aging: A reliability and security concern.Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi
2018IOLTSDetecting and Resolving Security Violations in Reconfigurable Scan Networks.Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodrguez Gmez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer
2017ETSSpecification and verification of security in reconfigurable scan networks.Michael A. Kochte, Matthias Sauer, Laura Rodrguez Gmez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich
2017ETSProbabilistic sensitization analysis for variation-aware path delay fault test evaluation.Marcus Wagner, Hans-Joachim Wunderlich
2017IOLTSEnergy-efficient and error-resilient iterative solvers for approximate computing.Alexander Schll, Claus Braun, Hans-Joachim Wunderlich
2017ITCAnalysis and mitigation or IR-Drop induced scan shift-errors.Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
2017VTSSpecial session on early life failures.Jyotirmoy V. Deshmukh, Wolfgang Kunz, Hans-Joachim Wunderlich, Sybille Hellebrand
2017VTSAging monitor reuse for small delay fault testing.Chang Liu, Michael A. Kochte, Hans-Joachim Wunderlich
2016ASPDACMixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2016DSNEfficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations.Alexander Schll, Claus Braun, Michael A. Kochte, Hans-Joachim Wunderlich
2016ETSFormal verification of secure reconfigurable scan network infrastructure.Michael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2016ETSETS 2015 best paper.Hans-Joachim Wunderlich, Peter C. Maxwell
2016IOLTSPushing the limits: How fault tolerance extends the scope of approximate computing.Hans-Joachim Wunderlich, Claus Braun, Alexander Schll
2016VTSFault tolerance of approximate compute algorithms.Hans-Joachim Wunderlich, Claus Braun, Alexander Schll
2015DATEOn-line prediction of NBTI-induced aging rates.Rafal Baranowski, Farshad Firouzi, Saman Kiamehr, Chang Liu, Mehdi Baradaran Tahoori, Hans-Joachim Wunderlich
2015DATEGPU-accelerated small delay fault simulation.Eric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich
2015ETSTesting visions.Hans-Joachim Wunderlich
2015ICCADSTRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures.Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jrg Henkel
2015IOLTSEfficient observation point selection for aging monitoring.Chang Liu, Michael A. Kochte, Hans-Joachim Wunderlich
2015IOLTSEfficient on-line fault-tolerance for the preconditioned conjugate gradient method.Alexander Schll, Claus Braun, Michael A. Kochte, Hans-Joachim Wunderlich
2014DACAdvanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures.Felix Reimann, Michael Gla, Jrgen Teich, Alejandro Cook, Laura Rodrguez Gmez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein
2014DACGUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems.Hongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jrg Henkel
2014DATENon-intrusive integration of advanced diagnosis features in automotive E/E-architectures.Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Gla, Felix Reimann, Laura Rodrguez Gmez, Thomas Russ, Jrgen Teich, Dominik Ull, Hans-Joachim Wunderlich
2014DATEBit-Flipping Scan - A unified architecture for fault tolerance and offline test.Michael E. Imhof, Hans-Joachim Wunderlich
2014DSNA-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units.Claus Braun, Sebastian Halder, Hans-Joachim Wunderlich
2014ETSDiagnosis of multiple faults with highly compacted test responses.Alejandro Cook, Hans-Joachim Wunderlich
2014ETSVariation-aware deterministic ATPG.Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker
2014ETSIncremental computation of delay fault detection probability for variation-aware test generation.Marcus Wagner, Hans-Joachim Wunderlich
2014ICCADData-parallel simulation for fast and accurate timing validation of CMOS circuits.Eric Schneider, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich
2014IOLTSArea-efficient synthesis of fault-secure NoC switches.Atefe Dalirsani, Michael A. Kochte, Hans-Joachim Wunderlich
2014ITCTest pattern generation in presence of unknown values based on restricted symbolic logic.Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker
2014ITCFAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects.Sybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich
2014VTSStructural Software-Based Self-Test of Network-on-Chip.Atefe Dalirsani, Michael E. Imhof, Hans-Joachim Wunderlich
2013DATEAccurate QBF-based test pattern generation in presence of unknown values.Stefan Hillebrecht, Michael A. Kochte, Dominik Erb, Hans-Joachim Wunderlich, Bernd Becker
2013DATEEfficient variation-aware statistical dynamic timing analysis for delay test applications.Marcus Wagner, Hans-Joachim Wunderlich
2013ETSScan pattern retargeting and merging with reduced access time.Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich
2013IOLTSEfficacy and efficiency of algorithm-based fault-tolerance on GPUs.Hans-Joachim Wunderlich, Claus Braun, Sebastian Halder
2013ITCModule diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jrg Henkel
2012ETSBuilt-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test.Alejandro Cook, Sybille Hellebrand, Hans-Joachim Wunderlich
2012ETSEfficient system-level aging prediction.Nadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich
2012ETSExact stuck-at fault classification in presence of unknowns.Stefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker
2012ICCDAcceleration of Monte-Carlo molecular simulations on hybrid computing architectures.Claus Braun, Stefan Holst, Hans-Joachim Wunderlich, Juan Manuel Castillo-Sanchez, Joachim Gross
2012IOLTSTransparent structural online test for reconfigurable systems.Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jrg Henkel, Hans-Joachim Wunderlich
2012ITCModeling, verification and pattern generation for reconfigurable scan networks.Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich
2012VTSA pseudo-dynamic comparator for error detection in fault tolerant architectures.D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich
2011DATESAT-based fault coverage evaluation in the presence of unknown values.Michael A. Kochte, Hans-Joachim Wunderlich
2011ETSStructural In-Field Diagnosis for Random Logic Circuits.Alejandro Cook, Melanie Elm, Hans-Joachim Wunderlich, Ulrich Abelein
2011ETSStructural Test for Graceful Degradation of NoC Switches.Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich
2011ETSTowards Variation-Aware Test Methods.Ilia Polian, Bernd Becker, Sybille Hellebrand, Hans-Joachim Wunderlich, Peter C. Maxwell
2011IOLTSFail-safety in core-based system design.Rafal Baranowski, Hans-Joachim Wunderlich
2011IOLTSSoft error correction in embedded storage elements.Michael E. Imhof, Hans-Joachim Wunderlich
2011ISLPEDSAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich
2011ITCP-PET: Partial pseudo-exhaustive test for high defect coverage.Abdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich
2010DACEfficient fault simulation on many-core processors.Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin
2010DATEBISD: Scan-based Built-In self-diagnosis.Melanie Elm, Hans-Joachim Wunderlich
2010DSNMassive statistical process variations: A grand challenge for testing nanoelectronic circuits.Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich
2010ETSAlgorithm-based fault tolerance for many-core architectures.Claus Braun, Hans-Joachim Wunderlich
2010ITCSystem reliability evaluation using concurrent multi-level simulation of structural faults.Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto
2010ITCParity prediction synthesis for nano-electronic gate designs.D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2010VTSLow-power test planning for arbitrary at-speed delay-test clock schemes.Christian G. Zoellin, Hans-Joachim Wunderlich
2009DATEA diagnosis algorithm for extreme space compaction.Stefan Holst, Hans-Joachim Wunderlich
2009DATETest exploration and validation using transaction level models.Michael A. Kochte, Christian G. Zoellin, Michael E. Imhof, Rauf Salimi Khaligh, Martin Radetzki, Hans-Joachim Wunderlich, Stefano Di Carlo, Paolo Prinetto
2009ETSTest Encoding for Extreme Response Compaction.Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich
2009ETSConcurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich
2009VTSRestrict Encoding for Mixed-Mode BIST.Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jrgen Schlffel, Friedrich Hapke, Andreas Glowatz
2008DACScan chain clustering for test power reduction.Melanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mding
2008DATEScan Chain Organization for Embedded Diagnosis.Melanie Elm, Hans-Joachim Wunderlich
2008ETSAdaptive Debug and Diagnosis without Fault Dictionaries.Stefan Holst, Hans-Joachim Wunderlich
2008ETSSelective Hardening in Early Design Steps.Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker
2008IOLTSIntegrating Scan Design and Soft Error Correction in Low-Power Applications.Michael E. Imhof, Hans-Joachim Wunderlich, Christian G. Zoellin
2008VTSSignature Rollback - A Technique for Testing Robust Circuits.Uranmandakh Amgalan, Christian Hachmann, Sybille Hellebrand, Hans-Joachim Wunderlich
2007DACScan Test Planning for Power Reduction.Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mding, Jens Leenstra
2007DDECSAnalyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.Philipp hler, Sybille Hellebrand, Hans-Joachim Wunderlich
2007ETSAdaptive Debug and Diagnosis without Fault Dictionaries.Stefan Holst, Hans-Joachim Wunderlich
2007ETSAn Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.Philipp hler, Sybille Hellebrand, Hans-Joachim Wunderlich
2007ITCProgrammable deterministic Built-In Self-Test.Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jrgen Schlffel, Laurent Souef
2006DATESoftware-based self-test of processors under power constraints.Jun Zhou, Hans-Joachim Wunderlich
2006ETSDeterministic Logic BIST for Transition Fault Testing.Valentin Gherman, Hans-Joachim Wunderlich, Jrgen Schlffel, Michael Garbers
2006ITCBIST Power Reduction Using Scan-Chain Disable in the Cell Processor.Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mding, Jens Leenstra
2005ETSFrom embedded test to embedded diagnosis.Hans-Joachim Wunderlich
2005FPLOn the Reliability Evaluation of SRAM-Based FPGA Designs.Olivier Hron, Talal Arnaout, Hans-Joachim Wunderlich
2005GISoftware-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschrnkung.Jun Zhou, Hans-Joachim Wunderlich
2005ISCASDevelopment of an audio player as system-on-a-chip using an open source platform.Pattara Kiatisevi, Luis Leonardo Azuara-Gomez, Rainer Dorsch, Hans-Joachim Wunderlich
2005VTSImplementing a Scheme for External Deterministic Self-Test.Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jrgen Schlffel
2004DATEImpact of Test Point Insertion on Silicon Area and Timing during Layout.Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich
2004ITCEfficient Pattern Mapping for Deterministic Logic BIST.Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers
2004ITCX-Masking During Logic BIST and Its Impact on Defect Coverage.Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
2002ETSRESPIN++ - deterministic embedded test.Lars Schfer, Rainer Dorsch, Hans-Joachim Wunderlich
2002ETSCombining deterministic logic BIST with test point insertion.Harald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich
2002ITCAdapting an SoC to ATE Concurrent Test Capabilities.Rainer Dorsch, Ramn Huerta Rivera, Hans-Joachim Wunderlich, Martin Fischer
2001DATEOn applying the set covering model to reseeding.Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Hans-Joachim Wunderlich
2001DATEUsing mission logic for embedded testing.Rainer Dorsch, Hans-Joachim Wunderlich
2001DATECircuit partitioning for efficient logic BIST synthesis.Alexander Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich
2001ETSReusing scan chains for test pattern decompression.Rainer Dorsch, Hans-Joachim Wunderlich
2001ITCTailoring ATPG for embedded testing.Rainer Dorsch, Hans-Joachim Wunderlich
2001ITCUsing a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schnemann, Thomas Schwarz, Hans-Joachim Wunderlich
2001ITCTwo-dimensional test data compression for scan-based deterministic BIST.Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
2001VTSA Modified Clock Scheme for a Low Power BIST Test Pattern Generator.Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2000DATEOptimal Hardware Pattern Generation for Functional BIST.Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
2000ITCNon-intrusive BIST for systems-on-a-chip.Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
2000ITCA mixed mode BIST scheme based on reseeding of folding counters.Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang
2000ITCApplication of deterministic logic BIST on industrial circuits.Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
1999DATESymmetric Transparent BIST for RAMs.Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik
1999EDCCTransparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich
1999ETSDeterministic BIST with partial scan.Gundolf Kiefer, Hans-Joachim Wunderlich
1999ITCMinimized power consumption for scan-based BIST.Stefan Gerstendrfer, Hans-Joachim Wunderlich
1999VTSError Detecting Refreshment for Embedded DRAMs.Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik
1998DATESelf-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich
1998ITCAccumulator based deterministic BIST.Rainer Dorsch, Hans-Joachim Wunderlich
1998ITCDeterministic BIST with multiple scan chains.Gundolf Kiefer, Hans-Joachim Wunderlich
1998VTSFast Self-Recovering Controllers.Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich
1997DATEFast controllers for data dominated applications.Andre Hertwig, Hans-Joachim Wunderlich
1997ITCUsing BIST Control for Pattern Generation.Gundolf Kiefer, Hans-Joachim Wunderlich
1997VTSPower Dissipation During Testing: Should We Worry About it?Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian
1996DATEDeterministic Pattern Generation for Weighted Random Pattern Testing.Birgit Reeb, Hans-Joachim Wunderlich
1996ICCADBit-flipping BIST.Hans-Joachim Wunderlich, Gundolf Kiefer
1996ITCMixed-Mode BIST Using Embedded Processors.Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
1995DATESynthesis of IHans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Caldern
1995ICCADPattern generation for a deterministic BIST scheme.Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich
1995ICCADTest register insertion with minimum hardware cost.Albrecht P. Stroele, Hans-Joachim Wunderlich
1994ICCADAn efficient procedure for the synthesis of fast self-testable controller structures.Sybille Hellebrand, Hans-Joachim Wunderlich
1994ITCSimulation Results of an Efficient Defect-Analysis Procedure.Olaf Stern, Hans-Joachim Wunderlich
1994ITCConfiguring Flip-Flops to BIST Registers.Albrecht P. Stroele, Hans-Joachim Wunderlich
1991DACA Unified Approach for the Synthesis of Self-Testable Finite State Machines.Bernhard Eschermann, Hans-Joachim Wunderlich
1991ITCA Common Approach to Test Generation and Hardware Verification Based on Temporal Logic.Thomas Kropf, Hans-Joachim Wunderlich
1990ITCGenerating pseudo-exhaustive vectors for external testing.Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl
1990ITCError masking in self-testable circuits.Albrecht P. Stroele, Hans-Joachim Wunderlich
1989ITCThe Pseudo-Exhaustive Test of Sequential Circuits.Sybille Hellebrand, Hans-Joachim Wunderlich
1988GIAutomatisierung des Entwurfs vollstndig testbarer Schaltungen.Sybille Hellebrand, Hans-Joachim Wunderlich
1988ITCMultiple Distributions for Biased Random Test Patterns.Hans-Joachim Wunderlich
1987DACOn Computing Optimized Input Probabilities for Random Tests.Hans-Joachim Wunderlich
1986DACOn fault modeling for dynamic MOS circuits.Hans-Joachim Wunderlich, Wolfgang Rosenstiel
1985DACPROTEST: a tool for probabilistic testability analysis.Hans-Joachim Wunderlich