IEEE European Test Symposium

ETS

CORE rank

CORE rank (raw)

Fields of research

Computer Systems Engineering

Papers indexed

1,163

1999–2026

Best Computer Systems Engineering conferences

Papers per year

199968 peak2026

Most published authors

ETS papers

1,163 records sourced from DBLP. Search titles, filter by year, sort by recency.

Year	Title	Authors
2010	A diagnostic test generation system and a coverage metric.	Yu Zhang, Vishwani D. Agrawal
2010	Scan based speed-path debug for a microprocessor.	Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz
2010	A shared BIST optimization methodology for memory test.	Lilia Zaourar, Jihane Alami Chentoufi, Yann Kieffer, Arnaud Wenzel, Frederic Grandvaux
2010	A transient error tolerant self-timed asynchronous architecture.	Masoud Zamani, Mehdi Baradaran Tahoori
2010	Hybrid test application in hybrid delay scan design.	Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue
2010	A multi-mode MEMS sensor design to support system test and health & usage monitoring applications.	Zhou Xu, Andrew Richardson, Lijie Li, Mark L. Begbie, D. Koltsov, ChangHai Wang
2010	On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.	Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis
2010	Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.	Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras
2010	Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach.	Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara
2010	Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.	Daniel Tille, Stephan Eggersgl, Rene Krenz-Baath, Jrgen Schlffel, Rolf Drechsler
2010	Defect filter for alternate RF test.	Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
2010	Predicting dynamic specifications of ADCs with a low-quality digital input signal.	Xiaoqin Sheng, Vincent Kerzerho, Hans G. Kerkhoff
2010	Diagnosis of full open defects in interconnect lines with fan-out.	Rosa Rodrguez-Montas, Daniel Arum, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman
2010	On the use of standard digital ATE for the analysis of RF signals.	Nicolas Pous, Florence Azas, Laurent Latorre, Jochen Rivoir
2010	Input test data volume reduction based on test vector chains.	Irith Pomeranz, Sudhakar M. Reddy
2010	Production test challenges for highly integrated mobile phone SOCs - A case study.	Frank Poehl, Frank Demmerle, Juergen Alt, Hermann Obermeir
2010	Full-circuit SPICE simulation based validation of dynamic delay estimation.	Ke Peng, Yu Huang, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor
2010	Configurable fault-tolerant link for inter-die communication in 3D on-chip networks.	Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi
2010	Test-architecture optimization for TSV-based 3D stacked ICs.	Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree
2010	On estimation of NBTI-Induced delay degradation.	Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
2010	On measurement uncertainty of ADC nonlinearities in oscillation-based test.	Peter Mrak, Anton Biasizzo, Franc Novak
2010	Test of embedded analog circuits based on a built-in current sensor.	Romn Mozuelos, Yolanda Lechuga, Mar Martnez, Salvador Bracho
2010	Adaptive test directions.	Peter C. Maxwell
2010	A two-layer SPICE model of the ATMEL TSTAC	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benot Godard, Gilles Festes, Laurent Vachez
2010	A new built-in IDDQ testing method using programmable BICS.	Samed Maltabas, Osman Kubilay Ekekon, Martin Margala

801–825 of 1,163← Previous Next →

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