| 2010 | Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications. | Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner |
| 2010 | Fast simulation based testing of anti-tearing mechanisms for small embedded systems. | Johannes Loinig, Christian Steger, Reinhold Weiss, Ernst Haselsteiner |
| 2010 | A distributed architecture to check global properties for post-silicon debug. | Erik Larsson, Bart Vermeulen, Kees Goossens |
| 2010 | Multivariate model for test response analysis. | Shaji Krishnan, Hans G. Kerkhoff |
| 2010 | Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. | Ho Fai Ko, Nicola Nicolici |
| 2010 | A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. | Hyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo |
| 2010 | Pipelined parallel test structure for mixed-signal SoCs. | Yang Jin, Hong Wang, Zhengliang Lv, Shiyuan Yang |
| 2010 | Test pattern selection to optimize delay test quality with a limited size of test set. | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara |
| 2010 | A low-cost built-in self-test scheme for an array of memories. | Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li |
| 2010 | A reconfigurable online BIST for combinational hardware using digital neural networks. | S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi |
| 2010 | Automated conformance evaluation of SystemC designs using timed automata. | Paula Herber, Marcel Pockrandt, Sabine Glesner |
| 2010 | Current-based testable design of level shifters in liquid crystal display drivers. | Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita |
| 2010 | A software-based self-test methodology for system peripherals. | Michelangelo Grosso, Wilson J. Prez H., Danilo Ravotto, Edgar E. Snchez, Matteo Sonza Reorda, Jaime Velasco-Medina |
| 2010 | Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. | Sezer Gren, H. Fatih Ugurdag, Okan Palaz |
| 2010 | Constructing augmented time compactors. | Emil Gizdarski |
| 2010 | Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. | Jose Luis Garcia-Gervacio, Vctor H. Champac |
| 2010 | Design and implementation of Automatic Test Equipment IP module. | S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich |
| 2010 | Setting test conditions for improving SRAM reliability. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | Multiple fault diagnosis in crossbar nano-architectures. | Navid Farazmand, Mehdi Baradaran Tahoori |
| 2010 | Calibration-enabled scalable built-in current sensor compatible with very low cost ATE. | Sachin Dileep Dasnurkar, Jacob A. Abraham |
| 2010 | A low-cost and scalable test architecture for multi-core chips. | Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li |
| 2010 | Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance. | Abhijit Chatterjee |
| 2010 | Microprocessor fault-tolerance via on-the-fly partial reconfiguration. | Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese |
| 2010 | Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. | Gaetan Canivet, P. Maistn, Rgis Leveugle, Frdric Valette, Jessy Cldire, Marc Renaudin |