| 2009 | Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation. | Sehun Kook, Vishwanath Natarajan, Abhijit Chatterjee, Shalabh Goyal, Le Jin |
| 2009 | Resource-Efficient Programmable Trigger Units for Post-Silicon Validation. | Ho Fai Ko, Nicola Nicolici |
| 2009 | Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead. | Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich |
| 2009 | Test Encoding for Extreme Response Compaction. | Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich |
| 2009 | Partial Scan Approach for Secret Information Protection. | Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara |
| 2009 | Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. | Kihyuk Han, Joonsung Park, Jae Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh |
| 2009 | Speed-Path Debug Using At-Speed Scan Test Patterns. | Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai |
| 2009 | Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections. | Olivier Ginez, Jean-Michel Portal, Christophe Muller |
| 2009 | Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment. | Frank-Uwe Faber, Matthias Beck, Markus Rudack, Olivier Barondeau, Thomas Rabenalt, Michael Gssel, Andreas Leininger |
| 2009 | Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. | Stephan Eggersgl, Rolf Drechsler |
| 2009 | Automatic Functional Stress Pattern Generation for SoC Reliability Characterization. | Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Snchez, Matteo Sonza Reorda |
| 2009 | Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. | Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar |
| 2009 | Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems. | Qais Al-Gayem, Hongyuan Liu, Andrew Richardson, Nick C. Burd |
| 2009 | Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links. | Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada |
| 2008 | Selective Hardening in Early Design Steps. | Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker |
| 2008 | Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design. | Vladimir A. Zivkovic, Frank van der Heyden, Guido Gronthoud, Frans G. M. de Jong |
| 2008 | Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. | Quming Zhou, Mihir R. Choudhury, Kartik Mohanram |
| 2008 | The Future Is Low Power and Test. | Thomas W. Williams |
| 2008 | A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. | Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja |
| 2008 | Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns. | Seongmoon Wang, Wenlong Wei |
| 2008 | Critical Path Selection for Delay Test Considering Coupling Noise. | Rajeshwary Tayade, Jacob A. Abraham |
| 2008 | Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters. | Rajarajan Senguttuvan, Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee |
| 2008 | The Role of Test in Circuits Built with Unreliable Components. | Antonio Rubio |
| 2008 | Risks for Signal Integrity in System in Package and Possible Remedies. | Daniele Rossi, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gian Pietro Vanalli |
| 2008 | Safe Fault Collapsing Based on Dominance Relations. | Irith Pomeranz, Sudhakar M. Reddy |