| 2007 | System-in-Package, a Combination of Challenges and Solutions. | Philippe Cauvet, Serge Bernard, Michel Renovell |
| 2007 | On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores. | Paolo Bernardi, Michelangelo Grosso, Ernesto Snchez, Matteo Sonza Reorda |
| 2007 | Electronics Design-for-Test: Past, Present and Future. | Ben Bennetts |
| 2006 | Enhancing Delay Fault Coverage through Low Power Segmented Scan. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi |
| 2006 | Retention-Aware Test Scheduling for BISTed Embedded SRAMs. | Qiang Xu, Baosheng Wang, F. Y. Young |
| 2006 | Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. | Gefu Xu, Adit D. Singh |
| 2006 | A DFT Architecture for Asynchronous Networks-on-Chip. | Xuan-Tu Tran, Jean Durupt, Franois Bertrand, Vincent Beroulle, Chantal Robach |
| 2006 | Low-Cost Online Testing of Asynchronous Handshakes. | Delong Shang, Alexandre Yakovlev, Frank P. Burns, Fei Xia, Alexandre V. Bystrov |
| 2006 | Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits. | Erik Schler, Daniel Scain Farenzena, Luigi Carro |
| 2006 | Innovation and Wealth Creation from Technology. | Robin Saxby |
| 2006 | Fault Injection-based Reliability Evaluation of SoPCs. | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-Garca, Celia Lpez-Ongil, Luis Entrena |
| 2006 | Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. | Wenjing Rao, Alex Orailoglu, Ramesh Karri |
| 2006 | Fault Collapsing for Transition Faults Using Extended Transition Faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | Convolutional Compactors with Variable Polynomials. | Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2006 | On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture. | Frank Poehl, Jan Rzeha, Matthias Beck, Michael Gssel, Ralf Arnold, Peter Ossimitz |
| 2006 | Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators. | Gildas Lger, Adoracin Rueda |
| 2006 | A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare. | Bernd Laquai, Martin Hua, Guido Schulze, Michael Braun |
| 2006 | Test-per-Clock Detection, Localization and Identification of Interconnect Faults. | Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
| 2006 | Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters. | Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham |
| 2006 | "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azas, Mariane Comte, Michel Renovell |
| 2006 | Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. | Kentaroh Katoh, Hideo Ito |
| 2006 | Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. | Yu-Jen Huang, Jin-Fu Li |
| 2006 | Single-Event Upset Analysis and Protection in High Speed Circuits. | Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto |
| 2006 | Soft-Error Rate Testing of Deep-Submicron Integrated Circuits. | Tino Heijmen, Andr Nieuwland |
| 2006 | Minimal March Tests for Dynamic Faults in Random Access Memories. | Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian |