| 2017 | A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms. | Morteza Hosseini, Rashidul Islam, Amey M. Kulkarni, Tinoosh Mohsenin |
| 2017 | ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding. | Chin Hau Hoo, Akash Kumar |
| 2017 | A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. | Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So |
| 2017 | Applying the Flask Security Architecture to Secure SoC Design. | Festus Hategekimana, Christophe Bobda |
| 2017 | Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a Board. | Jong Hun Han, Neelakandan Manihatty Bojan, Andrew W. Moore |
| 2017 | Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. | Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei |
| 2017 | FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. | Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong |
| 2017 | Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. | Jeffrey Goeders |
| 2017 | A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators. | Haohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang |
| 2017 | Using Runahead Execution to Hide Memory Latency in High Level Synthesis. | Shane T. Fleming, David B. Thomas |
| 2017 | Energy Efficient Loop Unrolling for Low-Cost FPGAs. | Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier |
| 2017 | Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration. | Ashutosh Dhar, Deming Chen |
| 2017 | Fine-Grained Acceleration of Binary Neural Networks Using Intel Xeon Processor with Integrated FPGA. | Philip Colangelo, Randy Huang, Enno Lbbers, Martin Margala, Kevin Nealis |
| 2017 | HLScope: High-Level Performance Debugging for FPGA Designs. | Young Kyu Choi, Jason Cong |
| 2017 | FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider. | Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael D. Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek |
| 2017 | A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs. | Ian J. Barge, Cristinel Ababei |
| 2017 | Relocating Encrypted Partial Bitstreams by Advance Task Address Loading. | Adewale Adetomi, Godwin Enemali, Tughrul Arslan |
| 2017 | Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulation. | Abedalmuhdi Almomany, B. Earl Wells, Ken-ichi Nishikawa |
| 2017 | A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation. | Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet |
| 2016 | Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. | Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, Andr DeHon |
| 2016 | High-Throughput and Energy-Efficient Graph Processing on FPGA. | Shijie Zhou, Charalampos Chelmis, Viktor K. Prasanna |
| 2016 | ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling. | Zhiyuan Yang, Caleb Serafy, Ankur Srivastava |
| 2016 | Improving Classification Accuracy of a Machine Learning Approach for FPGA Timing Closure. | Que Yanghua, Nachiket Kapre, Harnhua Ng, Kirvy Teo |
| 2016 | AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS. | Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow |
| 2016 | SynADT: Dynamic Data Structures in High Level Synthesis. | Zeping Xue, David B. Thomas |