| 2018 | DeltaRNN: A Power-efficient Recurrent Neural Network Accelerator. | Chang Gao, Daniel Neil, Enea Ceolini, Shih-Chii Liu, Tobi Delbruck |
| 2018 | FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method. | Sean Fox, David Boland, Philip Heng Wai Leong |
| 2018 | Improving FPGA Performance with a S44 LUT Structure. | Wenyi Feng, Jonathan W. Greene, Alan Mishchenko |
| 2018 | Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing Kernels. | Juan Escobedo, Mingjie Lin |
| 2018 | A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGA. | Jan Drre, Dario Paradzik, Holger Blume |
| 2018 | Software-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only). | Yankang Du, Qinrang Liu, Shuai Wei, Chen Gao |
| 2018 | Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only). | Nan Ding, Wei Zhang, Yanhua Ma, Zhenguo Gao |
| 2018 | SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only). | Luka Daoud, Muhammad Kamran Latif, Nader Rafla |
| 2018 | A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. | Steve Dai, Gai Liu, Zhiru Zhang |
| 2018 | Understanding Performance Differences of FPGAs and GPUs: (Abtract Only). | Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang |
| 2018 | K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only). | Jason Cong, Zhenman Fang, Yao Hu, Di Wu |
| 2018 | Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs: (Abstract Only). | Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis |
| 2018 | A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs. | Shenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter A. Milder |
| 2018 | An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). | Yuze Chi, Peipei Zhou, Jason Cong |
| 2018 | FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only). | Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong |
| 2018 | Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. | Jakub Cabal, Pavel Bencek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek |
| 2018 | Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only). | Matej Bartk, Sven Ubik, Pavel Kubalk, Toms Benes |
| 2018 | FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only). | Oluseyi A. Ayorinde, He Qi, Benton H. Calhoun |
| 2018 | FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS | Mikhail Asiatici, Damian Maiorano, Paolo Ienne |
| 2017 | A New Approach to Automatic Memory Banking using Trace-Based Address Mining. | Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang |
| 2017 | A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only). | Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li |
| 2017 | Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. | Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang |
| 2017 | Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only). | Zhipeng Zhao, James C. Hoe |
| 2017 | Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System. | Chi Zhang, Viktor K. Prasanna |
| 2017 | Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network. | Jialiang Zhang, Jing Li |