| 2015 | Enhancing Hardware Design Flows with MyHDL. | Keerthan Jaic, Melissa C. Smith |
| 2015 | FPGA Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals (Abstract Only). | Marko Jacovic, James Chacko, Doug Pfeil, Nagarajan Kandasamy, Kapil R. Dandekar |
| 2015 | An FPGA-Based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations (Abstract Only). | Yutaro Ishigaki, Ning Li, Yoichi Tomioka, Akihiko Miyazaki, Hitoshi Kitazawa |
| 2015 | Delay-Bounded Routing for Shadow Registers. | Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk |
| 2015 | 200 MS/s ADC implemented in a FPGA employing TDCs. | Harald Homulle, Francesco Regazzoni, Edoardo Charbon |
| 2015 | RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs. | Travis Haroldsen, Brent E. Nelson, Brad L. Hutchings |
| 2015 | A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only). | Gerardo Soria Garca, Adrian Pedroza de-la-Crz, Susana Ortega-Cisneros, Juan Jos Raygoza-Panduro, Eduardo Bayro-Corrochano |
| 2015 | Numerical Program Optimization for High-Level Synthesis. | Xitong Gao, George A. Constantinides |
| 2015 | Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only). | Pierre-Emmanuel Gaillardon, Gain Kim, Xifan Tang, Luca Gaetano Amar, Giovanni De Micheli |
| 2015 | On Implementation of LUT with Large Numbers of Inputs (Abstract Only). | Masahiro Fujita |
| 2015 | Formal Verification ATPG Search Engine Emulator (Abstract Only). | Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab |
| 2015 | System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. | Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica |
| 2015 | An Efficient and Flexible FPGA Implementation of a Face Detection System (Abstract Only). | Hichem Ben Fekih, Ahmed Elhossini, Ben H. H. Juurlink |
| 2015 | An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs (Abstract Only). | Hongyuan Ding, Miaoqing Huang |
| 2015 | Silicon Verification using High-Level Design Tools (Abstract Only). | Tomasz S. Czajkowski |
| 2015 | Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA. | Ren Chen, Sruja Siriyal, Viktor K. Prasanna |
| 2015 | MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only). | Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar |
| 2015 | The BEEcube Story: Lessons Learned from Running a FPGA Startup for the Past 7 Years. | Chen Chang |
| 2015 | Enhancements in UltraScale CLB Architecture. | Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer |
| 2015 | An Embedded FPGA Operating System Optimized for Vision Computing (Abstract Only). | Zhilei Chai, Jin Yu, Zhibin Wang, Jie Zhang, Haojie Zhou |
| 2015 | Rapid Prototyping of Wireless Physical Layer Modules Using Flexible Software/Hardware Design Flow. | James Chacko, Cem Sahin, Douglas Pfiel, Nagarajan Kandasamy, Kapil R. Dandekar |
| 2015 | Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware. | Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow |
| 2015 | Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits. | Dmitry Burlyaev, Pascal Fradet, Alain Girault |
| 2015 | A Novel Method for Enabling FPGA Context-Switch (Abstract Only). | Alban Bourge, Olivier Muller, Frdric Rousseau |
| 2015 | Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only). | Xu Bai, Yukihide Tsuji, Ayuka Morioka, Makoto Miyamura, Toshi Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada |