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ACM Int'l Symposium on Field Programmable Gate Arrays

FPGA

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

1,710

1992–2026

Papers per year

199294 peak2026

FPGA papers

1,710 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008When FPGAs are better at floating-point than microprocessors.Florent de Dinechin, Jrmie Detrey, Octavian Cret, Radu Tudoran
2008A hardware framework for the fast generation of multiple long-period random number streams.Ishaan L. Dalal, Deian Stefan
2008FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery.Luis Miguel Contreras-Medina, Ren de Jess Romero-Troncoso, Jose de Jesus Rangel-Magdaleno, Jesus Roberto Millan-Almaraz
2008Lithographic aerial image simulation with FPGA-based hardwareacceleration.Jason Cong, Yi Zou
2008Pattern-based behavior synthesis for FPGA resource reduction.Jason Cong, Wei Jiang
2008A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2008Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.Lerong Cheng, Yan Lin, Lei He
2008Efficient tiling patterns for reconfigurable gate arrays.Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley
2008Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne
2008An integrated debugging environment for FPGA computing platforms.Kevin Camera, Robert W. Brodersen
2008Reconfigurable computing for learning Bayesian networks.Narges Bani Asadi, Teresa H. Meng, Wing Hung Wong
2008Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.Amin Ansari, Keyvan Amiri
2008Architecture-specific packing for virtex-5 FPGAs.Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal
2007Post-route LUT output polarity selection for timing optimization.Kai Zhu
2007Integrating FPGAs in high-performance computing: the architecture and implementation perspective.Nathan Woods
2007High-level languages: the future or a passing fad?Michael J. Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen
2007A synthesizable datapath-oriented embedded FPGA fabric.Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton
2007A practical FPGA-based framework for novel CMP research.Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Teslyar, Daxia Ge, Christos Kozyrakis, Kunle Olukotun
2007The shunt: an FPGA-based accelerator for network intrusion prevention.Nicholas Weaver, Vern Paxson, Jos M. Gonzlez
2007Power-aware FPGA logic synthesis using binary decision diagrams.Kevin Oo Tinmaung, David Howland, Russell Tessier
2007Design of a logic element for implementing an asynchronous FPGA.Scott C. Smith
2007A versatile, low latency HyperTransport core.David Slogsnat, Alexander Giese, Ulrich Brning
2007Variation-aware routing for FPGAs.Satish Sivaswamy, Kia Bazargan
2007Integrating FPGAs in high-performance computing: programming models for parallel systems -- the programmer's perspective.Satnam Singh
2007Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.N. Pete Sedcole, Peter Y. K. Cheung
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