Skip to content

ACM Int'l Symposium on Field Programmable Gate Arrays

FPGA

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

1,710

1992–2026

Papers per year

199294 peak2026

FPGA papers

1,710 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008Measuring and modeling FPGA clock variability.N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors.Jose de Jesus Rangel-Magdaleno, Ren de Jess Romero-Troncoso, Luis Miguel Contreras-Medina, Arturo Garcia-Perez
2008CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan
2008A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2008A novel FPGA logic block for improved arithmetic performance.Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008From the bitstream to the netlist.Jean-Baptiste Note, ric Rannaud
2008Communication bottleneck in hardware-software partitioning.Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh
2008Mapping for better than worst-case delays in LUT-based FPGA designs.Kirill Minkovich, Jason Cong
2008A type system for static typing of a domain-specific language.Paul Edward McKechnie, Nathan A. Lindop, Wim Vanderbauwhede
2008Retrieving 3-d information with FPGA-based stream processing.Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri
2008High-throughput interconnect wave-pipelining for global communication in FPGAs.Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008Implementing high-speed string matching hardware for network intrusion detection systems.Atul Mahajan, Benfano Soewito, Sai K. Parsi, Ning Weng, Haibo Wang
2008High-quality, deterministic parallel placement for FPGAs on commodity hardware.Adrian Ludwin, Vaughn Betz, Ketan Padalia
2008TORCH: a design tool for routing channel segmentation in FPGAs.Mingjie Lin, Abbas El Gamal
2008The amorphous FPGA architecture.Mingjie Lin
2008Designing with extreme parallelism.Guy G. Lemieux, Tarek A. El-Ghazawi
2008Area and delay trade-offs in the circuit and architecture design of FPGAs.Ian Kuon, Jonathan Rose
2008HybridOS: runtime support for reconfigurable accelerators.John H. Kelm, Steven S. Lumetta
2008Configurable decoders with application in fast partial reconfiguration of FPGAs.Matthew Collin Jordan, Ramachandran Vaidyanathan
2008WireMap: FPGA technology mapping for improved routability.Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko
2008Fpga-based data acquisition system for a positron emission tomography (PET) scanner.Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck
2008Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.Michael T. Frederick, Arun K. Somani
2008Modeling routing demand for early-stage FPGA architecture development.Wei Mark Fang, Jonathan Rose
2008Extreme parallel architectures for the masses.Tarek A. El-Ghazawi, Guy G. Lemieux
2008Efficient ASIP design for configurable processors with fine-grained resource sharing.Quang Dinh, Deming Chen, Martin D. F. Wong
1,1261,150 of 1,710← PreviousNext →

Comparable venues

Other A*/A conferences filed under the same field of research.