| 2009 | Cholesky decomposition using fused datapath synthesis. | Sleyman Sirri Demirsoy, Martin Langhammer |
| 2009 | Computation reuse in domain-specific optimization of signal recognition. | Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang |
| 2009 | Revisiting bitwidth optimizations. | Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou |
| 2009 | Synthesis of reconfigurable high-performance multicore systems. | Jason Cong, Karthik Gururaj, Guoling Han |
| 2009 | Flexible multi-mode embedded floating-point unit for field programmable gate arrays. | Yee Jern Chong, Sri Parameswaran |
| 2009 | Fpga-based face detection system using Haar classifiers. | Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner |
| 2009 | CMOS vs Nano: comrades or rivals? | Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, Andr DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger |
| 2009 | A comparison of via-programmable gate array logic cell circuits. | Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang |
| 2009 | Diagonal tracks in FPGAs: a performance evaluation. | Sumanta Chaudhuri |
| 2009 | 3D configuration caching for 2D FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
| 2009 | Automatic bus macro placement for partially reconfigurable FPGA designs. | Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin |
| 2009 | Measuring and modeling variabilityusing low-cost FPGAs. | Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau |
| 2009 | Bus mastering PCI express in an FPGA. | Ray Bittner |
| 2009 | Customizable bit-width in an OpenMP-based circuit design tool. | Timothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent |
| 2009 | Emerging application domains: research challenges and opportunities for FPGAs. | Jason Helge Anderson |
| 2009 | Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. | Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani |
| 2009 | Parallel placement for FPGAs revisited. | Cristinel Ababei |
| 2008 | Vector processing as a soft-core CPU accelerator. | Jason Yu, Guy G. Lemieux, Christopher Eagleston |
| 2008 | FPGA interconnect design using logical effort. | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong |
| 2008 | Efficient FPGA implementation of qr decomposition using a systolic array architecture. | Xiaojun Wang, Miriam Leeser |
| 2008 | FPGA-optimised high-quality uniform random number generators. | David B. Thomas, Wayne Luk |
| 2008 | Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. | Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera |
| 2008 | Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals. | Keith So |
| 2008 | C is for circuits: capturing FPGA circuits as sequential code for portability. | Scott Sirowy, Greg Stitt, Frank Vahid |
| 2008 | A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design. | David Sheldon, Frank Vahid |