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ACM Int'l Symposium on Field Programmable Gate Arrays

FPGA

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

1,710

1992–2026

Papers per year

199294 peak2026

FPGA papers

1,710 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2009Data streaming and simd support for the microblaze architecture.Paul E. Marks, Cameron D. Patterson
2009Impact and compensation of correlated process variation on ring oscillator based puf.Abhranil Maiti, Patrick Schaumont
2009A high-performance FPGA architecture for restricted boltzmann machines.Daniel Le Ly, Paul Chow
2009VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose
2009A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.Edward C. Lin, Rob A. Rutenbar
2009High-performance, energy-efficient platforms using in-socket FPGA accelerators.Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta
2009Towards automated ECOs in FPGAs.Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
2009Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.Xinyu Li, Omar Hammami
2009Architectural enhancements in Stratix-IIIDavid M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan
2009High-performance, cost-effective heterogeneous 3D FPGA architectures.Roto Le, Sherief Reda, R. Iris Bahar
2009A novel BIST approach for testing input/output buffers in FPGAs.Lei Chen, Zhiquan Zhang, Zhiping Wen
2009A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.Dirk Koch, Christian Beckhoff, Jrgen Teich
2009FPGA technology mapping with encoded libraries andstaged priority cuts.Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox
2009A high performance fpga-based implementation of position specific iterated blast.Server Kasap, Khaled Benkrid, Ying Liu
2009FPGA implementation of real-time skin color detection with mean-based surface flattening.Seunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon
2009Large-scale wire-speed packet classification on FPGAs.Weirong Jiang, Viktor K. Prasanna
2009SmartOpt: an industrial strength framework for logic synthesis.Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton
2009PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions.Johnny Tsung Lin Ho, Guy G. Lemieux
2009FPGA-based front-end electronics for positron emission tomography.Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt
2009Closed-loop modeling of power and temperature profiles of FPGAs.Kanupriya Gulati, Sunil P. Khatri, Peng Li
2009SPR: an architecture-adaptive CGRA mapping tool.Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
2009FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.Rosemary M. Francis, Simon W. Moore
2009A 17ps time-to-digital converter implemented in 65nm FPGA technology.Claudio Favi, Edoardo Charbon
2009FPCNA: a field programmable carbon nanotube array.Chen Dong, Scott Chilstedt, Deming Chen
2009Implementation of the reconfiguration port scheduling on the erlangen slot machine.Florian Dittmann, Elmar Weber, Norma Montealegre
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