| 2010 | FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only). | Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay |
| 2010 | FPGA power reduction by guarded evaluation. | Jason Helge Anderson, Chirag Ravishankar |
| 2010 | The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton |
| 2009 | 32-bit floating-point FPGA gaussian elimination. | Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu |
| 2009 | A novel minloop SB design to improve FPGA routability. | JIanDe Yu, Jinmei Lai |
| 2009 | Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
| 2009 | The input-aware dynamic adaptation of area and performance for reconfigurable accelerator. | Like Yan, Gang Wang, Tianzhou Chen |
| 2009 | An intermediate hardware model with load/store unit for C to FPGA. | Akira Yamawaki, Masahiko Iwane |
| 2009 | N-port memory mapping for LUT-based FPGAs. | Zuo Wang, Feng Shi, Qi Zuo, Weixing Ji, Mengxiao Liu |
| 2009 | Clock power reduction for virtex-5 FPGAs. | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
| 2009 | Intel atom | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang |
| 2009 | Implementation of a genetic algorithm on a virtex-ii pro FPGA. | Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou |
| 2009 | HW/SW methodologies for synchronization in FPGA multiprocessors. | Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto |
| 2009 | A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. | David B. Thomas, Lee W. Howes, Wayne Luk |
| 2009 | Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
| 2009 | HMMer acceleration using systolic array based reconfigurable architecture. | Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu |
| 2009 | Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. | Alastair M. Smith, Steven J. E. Wilton, Joydip Das |
| 2009 | Making good points: application-specific pareto-point generation for design space exploration using statistical methods. | David Sheldon, Frank Vahid |
| 2009 | Choose-your-own-adventure routing: lightweight load-time defect avoidance. | Raphael Rubin, Andr DeHon |
| 2009 | Performance and power of cache-based reconfigurable computing. | Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig |
| 2009 | Fast and scalable packet classification using perfect hash functions. | Viktor Pus, Jan Korenek |
| 2009 | A parallel/vectorized double-precision exponential core to accelerate computational science applications. | Robin Pottathuparambil, Ron Sass |
| 2009 | A clustering framework for task partitioning based on function-level data usage analysis. | Sayyed Arash Ostadzadeh, Roel Meeuws, Kamana Sigdel, Koen Bertels |
| 2009 | Streaming implementation of a sequential decompression algorithm on an FPGA. | Gaurav Mittal, David Zaretsky, Prithviraj Banerjee |
| 2009 | Scalable don't-care-based logic optimization and resynthesis. | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang |