| 2005 | An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only). | Khaled Benkrid, Samir Belkacemi |
| 2005 | Dynamic reconfiguration in FPGA-based SoC designs (abstract only). | Roman Bartosinski, Martin Danek, Petr Honzk, Rudolf Matousek |
| 2005 | A framework for rule processing in reconfigurable network systems (abstract only). | Michael Attig, John W. Lockwood |
| 2005 | Soft error rate estimation and mitigation for SRAM-based FPGAs. | Ghazanfar Asadi, Mehdi Baradaran Tahoori |
| 2005 | 3D FPGAs: placement, routing, and architecture evaluation (abstract only). | Cristinel Ababei, Hushrav Mogal, Kia Bazargan |
| 2004 | Addressing application integrity attacks using a reconfigurable architecture. | Joseph Zambreno, Rahul Simha, Alok N. Choudhary |
| 2004 | Divide and concatenate: a scalable hardware architecture for universal MAC. | Bo Yang, Ramesh Karri, David A. McGrew |
| 2004 | In-system FPGA prototyping of an itanium microarchitecture. | Roland E. Wunderlich, James C. Hoe |
| 2004 | A VHDL MPEG-7 shape descriptor extractor. | Bret Woz, Andreas E. Savakis |
| 2004 | A constraints programming approach to communication scheduling on SoPC architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Maya B. Gokhale |
| 2004 | Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement. | Michael J. Wirthlin |
| 2004 | The SFRA: a corner-turn FPGA architecture. | Nicholas Weaver, John R. Hauser, John Wawrzynek |
| 2004 | An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAs. | Phan Cong Vinh, Jonathan P. Bowen |
| 2004 | Roving testing using new built-in-self-tester designs for FPGAs. | Vinay Verma, Shantanu Dutt |
| 2004 | FPGAs vs. CPUs: trends in peak floating-point performance. | Keith D. Underwood |
| 2004 | Power analysis and estimation tool integrated with XPOWER. | Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls |
| 2004 | Highly pipelined asynchronous FPGAs. | John Teifel, Rajit Manohar |
| 2004 | SPFD-based one-to-many rewiring. | Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi |
| 2004 | Incremental physical resynthesis for timing optimization. | Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou |
| 2004 | Buffer schemes for runtime reconfiguration of function variants in communication systems. | Helmut Steckenbiller, Rudi Knorr |
| 2004 | Exploration of pipelined FPGA interconnect structures. | Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck |
| 2004 | Using reconfigurability to achieve real-time profiling for hardware/software codesign. | Lesley Shannon, Paul Chow |
| 2004 | Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. | Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis |
| 2004 | A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures. | Remy Eskinazi Sant'Anna, Manoel Eusbio de Lima, Paulo Romero Martins Maciel |
| 2004 | An FPGA implementation of block truncation coding for gray and color images. | Sherif M. Saif, Hazem M. Abbas, Salwa M. Nassar |