| 2005 | The Stratix II logic and routing architecture. | David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose |
| 2005 | Design, layout and verification of an FPGA using automated tools. | Ian Kuon, Aaron Egier, Jonathan Rose |
| 2005 | Dual-Vt FPGA design for leakage power reduction (abstract only). | Akhilesh Kumar, Mohab Anis |
| 2005 | Energy-efficient FPGA interconnect architecture design (abstract only). | Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume |
| 2005 | 3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only). | Chul Kim, A. M. Rassau, Mike Myung-Ok Lee |
| 2005 | VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only). | Leos Kafka, Rafal Kielbik, Rudolf Matousek, Juan Manuel Moreno |
| 2005 | An FPGA-based VLIW processor with custom hardware execution. | Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster |
| 2005 | Soft multiprocessor systems for network applications (abstract only). | Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer |
| 2005 | Efficient static timing analysis and applications using edge masks. | Mike Hutton, David Karchmer, Bryan Archell, Jason Govig |
| 2005 | An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only). | Sven Heithecker, Rolf Ernst |
| 2005 | A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only). | Hassan Hassan, Mohab Anis, Mohamed I. Elmasry |
| 2005 | Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. | Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano |
| 2005 | An execution environment for reconfigurable computing (abstract only). | Wenyin Fu, Katherine Compton |
| 2005 | Reconfigurable computers: an empirical analysis (abstract only). | Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Allen Michalski, Osman Devrim Fidanci, Mohamed Taher, Esam El-Araby, Esmail Chitalwala, Proshanta Saha |
| 2005 | 64-bit floating-point FPGA matrix multiplication. | Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev |
| 2005 | The effect of post-layout pin permutation on timing. | Yuzheng Ding, Peter Suaris, Nan-Chi Chou |
| 2005 | Floating-point sparse matrix-vector multiply for FPGAs. | Michael DeLorimier, Andr DeHon |
| 2005 | Design of programmable interconnect for sublithographic programmable logic arrays. | Andr DeHon |
| 2005 | Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). | Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel |
| 2005 | Instruction set extension with shadow registers for configurable processors. | Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang |
| 2005 | Simultaneous timing-driven placement and duplication. | Gang Chen, Jason Cong |
| 2005 | Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only). | Bryan Catanzaro, Brent E. Nelson |
| 2005 | Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2005 | Rapid prototyping of a test harness for forward error correcting codes (abstract only). | Edward Brown, James Irvine, Bill Wilkie |
| 2005 | Dynamic hardware multiplexing for coarse grain reconfigurable architectures. | Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon |