| 2004 | Dynamically reconfigurable architecture for high-throughput processing of data centric applications. | Magesh Sadasivam, Sangjin Hong |
| 2004 | An FPGA implementation of bene permutation networks. | Anatole D. Ruslanov, Jeremy R. Johnson |
| 2004 | An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. | Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee |
| 2004 | Evaluation of low-leakage design techniques for field programmable gate arrays. | Arifur Rahman, Vijay Polavarapuv |
| 2004 | On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. | Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner |
| 2004 | A high performance 32-bit ALU for programmable logic. | Paul Metzgen |
| 2004 | FPGA implementation of a high speed network interface card for optical burst switched networks. | Pronita Mehrotra, Mrugendra Singhai, Mike Pratt, Mark Cassada, Patrick Hamilton |
| 2004 | SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. | A. Manoj Kumar, B. Jayaram, V. Kamakoti |
| 2004 | Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. | Sergio Lpez-Buedo, Eduardo I. Boemo |
| 2004 | Routing architecture for multi-context FPGAs. | Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi |
| 2004 | Fast adders in modern FPGAs. | Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris |
| 2004 | Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. | Fei Li, Yan Lin, Lei He, Jason Cong |
| 2004 | Online placement infrastructure to support run-time reconfiguration. | Brian Leonard, Jeff Young, Ron Sass |
| 2004 | Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. | Jae-Jin Lee, Gi-Yong Song |
| 2004 | Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. | Ian Kuon, Aaron Egier, Jonathan Rose |
| 2004 | FPGA-based supercomputing: an implementation for molecular dynamics. | Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow |
| 2004 | A reconfigurable unit for a clustered programmable-reconfigurable processor. | Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter |
| 2004 | Low energy FPGA interconnect design. | Rohini Krishnan, Jos Pineda de Gyvez, Martijn T. Bennebroek |
| 2004 | An embedded true random number generator for FPGAs. | Paul Kohlbrenner, Kris Gaj |
| 2004 | A compiled accelerator for biological cell signaling simulations. | John F. Keane, Christopher Bradley, Carl Ebeling |
| 2004 | Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. | Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike |
| 2004 | High level area, delay and power estimation for FPGAs. | Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee |
| 2004 | Automatic discovery, selection, and specialization of modules in RCADE. | Ranjesh G. Jaganathan, Matthew Simpson, Ron Sass |
| 2004 | Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. | Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Mnner, Matthias Mller |
| 2004 | The gigahertz FPGA: design consideration and applications. | Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald |